 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| ?products and specifications discussed here in are for evaluation and re ference purposes only and are subject to change by micron without notice. products are only warranted by micron to meet micron?s production data sheet specifications. draft 5/19/2008 8, 16, 32, 64gb nand flash memory features micron confidential and proprietary advance ? pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__1.fm -rev. 1.9 5/08 en 1 ?2007 micron technology, inc. all rights reserved. nand flash memory mt29f8g08aaawp, mt29f16g08daawp, mt29f32g08faawp, MT29F8G08AAAC4, mt29f16g 08eaac4, mt29f32g08gaac4, mt29f8g08aaac6, mt29f16g 08eaac6, mt29f32g08gaac6, mt29f64g08kaac6 features ? open nand flash interf ace (onfi) 1.0 compliant ? single-level cell (slc) technology ? organization ? page size: x8: 4,314 bytes (4,096 + 218 bytes) ? block size: 64 pages (256k + 13k bytes) ? plane size: 2,048 blocks ? device size: 8gb: 4,096 blocks; 16gb: 8,192 blocks; 32gb: 16,384 blocks; 64gb: 32,768 blocks ?read performance ? random read: 25s ? sequential read: 20ns ?write performance ? program page: 250s (typ) ? block erase: 1.5ms (typ) ?endurance ? 100,000 program/erase cycles (1-bit ecc 1 ) ? data retention: 10 years ? first block (block address 00h) guaranteed to be valid when shipped from factory 1 ? industry-standard basic nand flash command set ? advanced command set ? program page cache mode ? page read cache mode ? one-time programmable (otp) commands ? two-plane commands ? interleaved die operations ? read unique id (contact factory) ? operation status byte provides a software method of detecting: ? operation completion ? pass/fail condition ? write-protect status ? ready/busy# (r/b#) signal provides a hardware method of detecting program or erase cycle completion ? wp# signal: entire device hardware write protect ? reset required after power-up ? internal data move operations supported within the plane from which data is read figure 1: 48-pin tsop type 1 notes: 1. for details, see ?error management? on page 89. 2. for part numbering and markings, see figure 2 on page 2. options ?density 2 ? 8gb, 16gb, 32gb, 64gb ? device width: x8 ? configuration: # of die # of ce# # of r/b# i/o tsop/lga 11 1 common tsop 22 2 common tsop 42 2 common lga 22 2 separate lga 42 2 separate lga 84 4 separate ?v cc : 2.7?3.6v ?package: ? 48 tsop type i (lead-free plating) ? 52-pad lga ? operating temperature: ? commercial temperature (0c to 70c) ? extended temperature (?40c to +85c)
draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__1.fm -rev. 1.9 5/08 en 2 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory part numbering information micron confidential and proprietary advance part numbering information micron nand flash devices ar e available in several different configurations and densi- ties (see figure 2). figure 2: part number chart valid part number combinations after building the part number from the part numbering chart, verify that the part number is offered and valid by using the micron parametric part search web site at www.micron.com/products/parametric . if the device required is not on this list, contact the factory. mt 29f 8g 08 a a a wp es :a micron technology product family 29f = single-supply nand flash memory density 8g = 8gb 16g = 16gb 32g = 32gb 64g = 64gb device width 08 = 8 bits operating voltage range a = 3.3v (2.7C3.6v) design revision a = first revision production status blank = production es = engineering sample ms = mechanical sample qs = qualification sample operating temperature range blank = commercial (0c to +70c) et = extended (C40 to +85c) reserved for future use blank nand flash performance blank = standard package code c4 = 52-pad vlga c6 = 52-pad llga wp = 48-pin tsop i (lead-free) feature set a = feature set a classification # of die # of ce# # of r/b# i/o a 1 1 1 common d 2 2 2 common e 2 2 2 separate f 4 2 2 common g 4 2 2 separate k 8 4 4 separate draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51atoc.fm -rev. 1.9 5/08 en 3 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory table of contents micron confidential and proprietary advance table of contents features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 part numbering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 valid part number combinations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 general description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 architecture . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 array organization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 bus operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 control signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 ready/busy# . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 time constants . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 command definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 page read 00h-30h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 random data read 05h-e0h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 read id 90h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 read parameter page ech . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 read status 70h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 page read cache mode operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 page read cache mode sequential 31h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 page read cache mode random 00h-31h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 page read cache mode last 3fh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 program operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 program page 80h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 serial data input 80h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 random data input 85h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 program page cache mode 80h-15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 internal data move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 read for internal data move 00h-35h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 program for internal data move 85h-10h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 block erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 block erase 60h-d0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 one-time programmable (otp) area . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 otp data program a0h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 otp data protect a5h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 otp data read afh-30h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 features operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 get features eeh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 set features efh . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 two-plane operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 two-plane addressing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 two-plane page read 00h-00h-30h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 two-plane random data read 06h-e 0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 two-plane program page 80h-11h-80h-10h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 two-plane program page cache mode 80h-11h-80h-15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 two-plane internal data move 00h-00h-35h/8 5h-11h-85h-10h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51atoc.fm -rev. 1.9 5/08 en 4 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory table of contents micron confidential and proprietary advance two-plane read for internal data move 00h -00h-35h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 two-plane program for internal data move 85h-11h-85h-10h. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 two-plane block erase 60h-d1h-60h-d0h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 two-plane/multiple-die read status 78h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 interleaved die operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 interleaved page read operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 interleaved two-plane page read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69 interleaved program page operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 interleaved program page cache mode operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 interleaved two-plane program page operation. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72 interleaved two-plane program page cache mo de operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74 interleaved read for internal data move operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 76 interleaved two-plane read for internal da ta move operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78 interleaved program for internal data move operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 interleaved two-plane program for internal data move operations . . . . . . . . . . . . . . . . . . . . . . . . . . . 80 interleaved block erase operations. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 interleaved two-plane block erase operations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83 reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 reset ffh. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 84 write protect operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 error management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 v cc power cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 timing diagrams. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 tsop package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 vlga package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 llga package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51alof.fm -rev. 1.9 5/08 en 5 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory list of figures micron confidential and proprietary advance list of figures figure 1: 48-pin tsop type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 figure 2: part number chart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 figure 3: pin assignment (top view) 48-pin tsop type 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 figure 4: pad assignment (top view) 52-pad vlga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 figure 5: pad assignment (top view) 52-pad llga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 figure 6: nand flash functional block diag ram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 figure 7: memory map (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 figure 8: array organization for 8gb and 16gb x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 figure 9: array organization for 32gb and 64gb x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 figure 10: ready/busy# open drain . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 figure 11: tfall and trise . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 12: iol vs. rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 13: tc vs. rp . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 figure 14: page read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 figure 15: random data read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 16: read id operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 figure 17: read parameter page (ech) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 figure 18: status register operation for re ad status . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 figure 19: page read cache mode operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 figure 20: program and read status operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 figure 21: random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 figure 22: program page cache mo de example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 figure 23: internal data move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 figure 24: internal data move with opti onal data output and random data input . . . . . . . . . . . . . . . . . 41 figure 25: block erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 figure 26: otp data program . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 figure 27: otp program with random data in put . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 figure 28: otp data protect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 figure 29: otp data read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 figure 30: otp data read with random data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 figure 31: get features operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 figure 32: set features operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 52 figure 33: two-plane page read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 figure 34: two-plane page read with random data read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 figure 35: two-plane program page . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 figure 36: two-plane program page with random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 figure 37: two-plane program page cache mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 figure 38: two-plane internal data move . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 figure 39: two-plane internal data move with two-plan e random data read . . . . . . . . . . . . . . . . 63 figure 40: two-plane internal data move with random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 figure 41: two-plane block erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 figure 42: two-plane/multiple-die read status cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 figure 43: interleaved page read with status register monitori ng . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 figure 44: interleaved two-plane page read with status register monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . 7 0 figure 45: interleaved program page with status register monito ring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 figure 46: interleaved program page cache mode with status register monitoring . . . . . . . . . . . . . . . . . . . 71 figure 47: interleaved two-plane program pa ge with status register monitoring . . . . . . . . . . . . . . . . . . . . . 73 figure 48: interleaved two-plane prog ram page cache mode with status re gister monitoring . . . . . . . 75 figure 49: interleaved read for internal data move with stat us register monitoring . . . . . . . . . . . . . . . . . . 77 figure 50: interleaved two-plane read for internal data move with status register monitoring . . . . . 79 figure 51: interleaved program for internal data move with status register monitoring . . . . . . . . . . . . . 80 figure 52: interleaved two-plane pr ogram for internal data move with status register monitoring . 81 figure 53: interleaved block erase with stat us register monitoring . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 figure 54: interleaved two-plane block erase with status register monitoring . . . . . . . . . . . . . . . . . . . . . . . 83 figure 55: reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 figure 56: erase enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51alof.fm -rev. 1.9 5/08 en 6 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory list of figures micron confidential and proprietary advance figure 57: erase disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 58: program enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 59: program disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 figure 60: program for internal data move enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 61: program for internal data move disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 62: two-plane erase enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 63: two-plane erase disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 figure 64: two-plane program enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 65: two-plane program disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 66: two-plane program for internal data move enable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 67: two-plane program for internal data move disable . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 figure 68: ac waveforms during power transi tions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 figure 69: command latch cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 70: address latch cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96 figure 71: input data latch cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97 figure 72: serial access cycle after read . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 73: serial access cycle after read (e do mode) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98 figure 74: read status cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 75: two-plane/multiple-die read stat us operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99 figure 76: page read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 77: read operation with ce# ?don?t care? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100 figure 78: random data read operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101 figure 79: page read cache mode operation, part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102 figure 80: page read cache mode operation, part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 figure 81: page read cache mode operation without r/b#, part 1 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 figure 82: page read cache mode operation without r/b#, part 2 of 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105 figure 83: read id operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 84: program page operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106 figure 85: program op eration with ce# ?don?t care? . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 figure 86: program page op eration with random data input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 figure 87: internal data move operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 88: program page cache mode operat ion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108 figure 89: program page cache mo de operation ending on 15h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 figure 90: block erase operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 91: reset operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110 figure 92: 48-pin tsop type 1 (wp package code) package diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 figure 93: 52-pad vlga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112 figure 94: 52-pad llga . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51alot.fm -rev. 1.9 5/08 en 7 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory list of tables micron confidential and proprietary advance list of tables table 1: signal descriptions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 table 2: operational example (x8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 table 3: array addressing: 8gb and 16gb x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 table 4: array addressing: 32gb and 64gb x8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 table 5: mode selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 table 6: command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 table 7: two-plane command set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 table 8: device id and configuration codes for address 00h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 table 9: device id and configuration codes for address 20h . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 table 10: parameter page data structure . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 table 11: status register bit definition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 table 12: features table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 table 13: feature address 01h: timing mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 14: feature address 80h: programmable i/o drive strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 table 15: feature address 81h: programmable r/b# pull-down strength . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 table 16: status register contents after re set operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 table 17: error management details . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89 table 18: absolute maximum ratings by device . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 19: recommended operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 table 20: device dc and operating characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 21: valid blocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92 table 22: capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 23: test conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 24: ac characteristics: command, data, and address input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93 table 25: ac characteristics: normal operat ion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 table 26: program/erase characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95 draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 8 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory general description micron confidential and proprietary advance general description nand flash technology provides a cost-effec tive solution for applications requiring high-density, solid-state storage. the mt29f8g is an 8gb nand flash memory device. the mt29f16 is a two-die stack that operat es as two independent 8gb devices. the mt29f32g is a four-die stack that operates as two independent 16gb devices, providing a total storage capacity of 32gb in a single, space-saving package. mt29f64g is an eight- die stack that operates as four independ ent 16gb devices, providing a total storage capacity of 64gb in a single , space-saving package. micron ? nand flash devices include standard nand flash fe atures as well as new featur es designed to enhance sys- tem-level performance. micron nand flash devices use a highly multiplexed 8-bit bus (i/o[7:0]) to transfer data, addresses, and instructions. the five command pins (cle, ale, ce#, re#, we#) implement the nand flash command bus inte rface protocol. two additional pins con- trol hardware write protection (wp# ) and monitor device status (r/b#). this hardware interface creates a low-pin-coun t device with a standard pinout that is the same from one density to another, allowing future upgrades to higher densities with- out board redesign. the mt29f8g, mt29f16g, mt29f32g, and mt29 f64g devices contain two planes per die, for a total of two or four planes. each plane consists of 2,048 blocks. each block is subdivided into 64 programmab le pages. each page consis ts of 4,314 bytes. the pages are further divided into a 4,096-byte data st orage region with a separate 218-byte area. the 218-byte area is typically used for error management functions. the contents of each page can be programmed in t prog, and an entire block can be erased in t bers. on-chip control logic automate s program and erase operations to maximize cycle endurance. program/erase endurance is specified at 100,000 cycles when using appropriate error correction code (ecc) and error management. the mt29f8g, mt29f16g, mt29f32g, and mt29f 64g are onfi 1.0-compliant devices. the onfi 1.0 specification is available at www.onfi.org . draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 9 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory general description micron confidential and proprietary advance figure 3: pin assignment (top view) 48-pin tsop type 1 notes: 1. ce2# and r/b2# on 16gb and 32gb devices only. thes e pins are nc for other configura- tions. 2. these v cc and v ss pins are for compatibility with onfi 1.0. if not supplying v cc or v ss to these pins, do not use them. x8 nc nc nc nc nc r/b2# 1 r/b# re# ce# ce2# 1 nc vcc vss nc nc cle ale we# wp# nc nc dnu nc nc x8 dnu/vss 2 nc nc nc i/o7 i/o6 i/o5 i/o4 nc dnu/vcc 2 dnu vcc vss nc dnu/vcc 2 nc i/o3 i/o2 i/o1 i/o0 nc nc nc dnu/vss 2 1 z 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 10 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory general description micron confidential and proprietary advance figure 4: pad assignment (top view) 52-pad vlga notes: 1. these signals are availabl e only on the 16gb and 32gb de vices. these pads are nc for other configurations. nc nc dnu dnu/ v ss nc nc nc nc dnu dnu dnu/ v ss nc nc ale i/o0-2 1 i/o1-2 1 i/o2-2 1 dnu/ v cc a b c d e f g h j k l m n v ss wp# i/o1 i/o3 v ss cle we# i/o0 i/o2 v ss i/o3-2 1 ce# ce2# 1 r/b# wp2# 1 i/o6 i/o4 i/o4-2 1 v cc re2# 1 v ss i/o7 i/o5 v cc nc re# r/b2# 1 i/o7-2 1 i/o6-2 1 i/o5-2 1 dnu/ v cc to p view, pads down 0 1 2 3 4 5 6 7 8 oa ob oc od oe of we2# 1 cle2 1 ale2 1 draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 11 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory general description micron confidential and proprietary advance figure 5: pad assignment (top view) 52-pad llga notes: 1. these signals are availabl e only on the 16gb, 32gb, and 64gb devices. these pads are nc for other configurations. 2. these signals are avai lable only on the 64gb device. these pads are nc for other configu- rations. nc dnu dnu/ v ss nc nc nc dnu dnu dnu/ v ss nc ale we2# 1 i/o0-2 1 i/o1-2 1 i/o2-2 1 dnu/ v cc a b c d e f g h j k l m n v ss ale2 1 wp# i/o1 i/o3 v ss cle cle2 1 we# i/o0 i/o2 v ss i/o3-2 1 ce# ce2# 1 r/b# wp2# 1 i/o6 i/o4 i/o4-2 1 v cc re2# 1 v ss i/o7 i/o5 v cc re# r/b2# 1 i/o7-2 1 i/o6-2 1 i/o5-2 1 dnu/ v cc to p view, pads down 0 1 2 3 4 5 6 7 8 oa ob oc od oe of r/b4# 2 2 ce4# 2 r/b3# 2 ce3# 2 nc draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 12 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory general description micron confidential and proprietary advance table 1: signal descriptions symbol type description ale, ale2 input address latch enable: during th e time ale is high, address information is transferred from i/o[7:0] into the on-chi p address register on th e rising edge of we# . when address information is not being loaded, ale should be driven low. ce#, ce2#, ce3#, ce4# input chip enable: this gates tran sfers between the host system and the nand flash device. after the device starts a program or erase operation, ce# can be de-asserted. for the 16gb configuration, ce# controls the first 8gb of memo ry; ce2# contro ls the second 8gb of memory. for the 32gb configuration, ce# controls the first 16gb of memory; ce2# controls the second 16gb of memo ry. for the 64gb configuration, ce# controls the first 16gb of memory; ce2# controls the second 16gb of memory; ce3# controls the third 16gb of memory; ce4# controls the fourth 16gb of memory. see ?bus operation,? starting on page 17, for additional operational details. cle, cle2 input command latch enable: when cle is hi gh, information is transferred from i/o[7:0] to the on-chip command register on the rising edge of we#. when command information is not being loaded, cle should be driven low. re#, re2# input read enable: this gates transfers from the nand flash device to the host system. we#, we2# input write enable: this gates transfers from the host system to the nand flash device. wp#, wp2# input write protect: pin protects against inadve rtent program and erase operations. all program and erase operations are disabled when wp# is low. i/o[7:0], i/o[7-2:0-2] (x8) i/o data inputs/outputs: the bidirectional i/ os transfer address, data, and instruction information. data is output only during read operations; at other times the i/os are inputs. r/b#, r/b2#, r/b3#, r/b4# output ready/busy: this is an open-dra in, active-low output, that uses an external pull-up resistor. the pin is used to indicate when the chip is processing a program or erase operation. it is also used during a read operation to indicate when data is being transferred from the array into the serial data register. once these operat ions have completed, r/ b# returns to the high- impedance state. in the 16gb configuration, r/b# is for the 8gb of memory enabled by ce#; r/b2# is for the 8gb of memory enabled by ce2#. in the 32gb configuration, r/b# is for the 16gb of memory enabled by ce#; r/b2# is for the 16gb of memory enabled by ce2#. in the 64gb configuration, r/b# is for the 16gb of memory enabled by ce#; r/b2# is for the 16gb of memory enabled by ce2#; r/b3# is for the 16gb of memory enab led by ce3#; r?b4# is for the 16gb of memory enabled by ce4#. v cc supply v cc : power supply pin. v ss supply v ss : ground connection. nc ? no connect: ncs are not intern ally connected. they can be driven or left unconnected. dnu ? do not use: dnus must be left disconnected. draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 13 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory architecture micron confidential and proprietary advance architecture these devices use nand flash electrical and command interfaces. data, commands, and addresses are multiplexed onto the same pins and received by i/o control circuits. this provides a memory device with a low pin count. the commands received at the i/o control circuits are latched by a command register and are transferred to control logic circuits for generating internal signals to control device operations. the addresses are latched by an address register and sent to a row decoder or a column decoder to select a row address or a column address, respectively. the data are transferred to or from the nand flash memory array, byte by byte (x8), through a data register and a cache register. the cache register is closest to i/o control circuits and acts as a data buffer for the i/o data, whereas the data register is closest to the memory array and acts as a data buffer for the nand flash memory array operation. the nand flash memory array is programmed and read in page-based operations and is erased in block-based operations. during normal page operations, the data and cache registers are tied together and act as a single register. during cache operations, the data and cache registers operate independen tly to increase data throughput. these devices also have a status register th at reports the status of device operation. figure 6: nand flash functional block diagram addressing nand flash devices do not contain dedicate d address pins. addresses are loaded using a 5-cycle sequence as shown in table 3 on pa ge 15. see figure 7 on page 14 for additional memory mapping and addressing details. address register data register cache register status register command register ce# v cc v ss cle ale we# re# wp# i/ox control logic i/o control r/b# row decode column decode nand flash array (2 planes) draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 14 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory memory mapping micron confidential and proprietary advance memory mapping figure 7: memory map (x8) note: as shown in table 3 on page 15, the three mo st significant bits in the high nibble of address cycle 2 are not assigned; however, th ese 3 bits must be held low during the address cycle to ensure that the address is interpreted correctly by the nand flash device. these extra bits are accounted for in address cycle 2 even though they do not have address bits assigned to them. the 13-bit column address is capable of addres sing from 0 to 8,191 by tes, however, only bytes 0 through 4,313 are valid. bytes 4,314 through 8,191 of each page are ?out of bounds,? do not exist in the device, and cannot be addressed. table 2: operational example (x8) block page min address in page max address in page out of bounds addresses in page 0 0 0x0000000000 0x00000110d9 0x00000010da?0x0000001fff 0 1 0x0000010000 0x00000110d9 0x00000110da?0x0000011fff 0 2 0x0000020000 0x00000210d9 0x00000210da?0x0000021fff ?? ? ? 4,095 62 0x03fffe0000 0x03fffe 10d9 0x03fffe10da?0x03fffe1fff 4,095 63 0x03ffff0000 0x03ffff1 0d9 0x03ffff10da?0x03ffff1fff ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? ? blocks 8gb, 16gb: ba[17:6] 32gb, 64gb: ba[18:6] pages pa[5:0] bytes ca[12:0] 012 012 63 0 1 2 4,095 ? ? ? 4,313 4,095 32gb, 64gb: 8,191 spare area draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 15 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory array organization micron confidential and proprietary advance array organization figure 8: array organization for 8gb and 16gb x8 notes: 1. for the 16gb mt29f16g08d, the 8gb array organization shown here applies to each chip enable (ce# and ce2#). notes: 1. block address concatenat ed with page address = actual page address. cax = column address; pax = page address; bax = block address. 2. column address 4,313 (10d9h) is the maximum valid column address. 3. plane select bit: 0 = plane of even-numbered blocks 1 = plane of odd-numbered blocks table 3: array addressing: 8gb and 16gb x8 cycle i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 first ca7 ca6 ca5 ca4 ca3 ca2 ca1 ca0 second low low low ca12 ca11 ca10 ca9 ca8 third ba7 ba6 3 pa5 pa4 pa3 pa2 pa1 pa0 fourth ba15 ba14 ba13 ba12 ba11 ba10 ba9 ba8 fifth low low low low low low ba17 ba16 cache register data register 2,048 blocks per plane 4,096 blocks per device 1 block 1 block i/o0 i/o7 1 page = (4k + 218 bytes) 1 block = (4k + 218) bytes x 64 pages = (256k + 13k) bytes 1 plane = (256k + 13k) bytes x 2,048 blocks = 4,304mb 1 device = 4,314mb x 2 planes = 8,608mb plane of even-numbered blocks (0, 2, 4, 6, ..., 4,092, 4,094) plane of odd-numbered blocks (1, 3, 5, 7, ..., 4,093, 4,095) 218 4,096 218 4,314 bytes 4,314 bytes 218 218 4,096 4,096 4,096 draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 16 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory array organization micron confidential and proprietary advance figure 9: array organization for 32gb and 64gb x8 notes: 1. die 0, plane 0: ba18 = 0; ba6 = 0 die 0, plane 1: ba 18 = 0; ba6 = 1 die 1, plane 0: ba 18 = 1; ba6 = 0 die 1, plane 1: ba 18 = 1; ba6 = 1 2. for the 32gb mt29f32g08f and mt29f32g08g devices, the 16gb array organization shown here applies to each chip enable (ce# and ce2#). 3. for the 64gb mt29f64g08k device, the 16gb array organization sh own here applies to each chip enable (ce#, ce2#, ce3#, and ce4#). notes: 1. cax = column address; pax = page address; bax = block address. 2. column address 4,313 (10d9h) is the maximum valid column address. 3. plane select bit: 0 = plane of even-numbered blocks 1 = plane of odd-numbered blocks 4. die select bit: 0 = 0?8gb 1 = 8gb?16gb. table 4: array addressing: 32gb and 64gb x8 cycle i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 first ca7ca6ca5ca4ca3ca2ca1ca0 second low low low ca12 ca11 ca10 ca9 ca8 third ba7 ba6 3 pa5 pa4 pa3 pa2 pa1 pa0 fourth ba15 ba14 ba13 ba12 ba11 ba10 ba9 ba8 fifth low low low low low ba18 4 ba17 ba16 cache register data register 2,048 blocks per plane 4,096 blocks per die 1 block 1 block plane 0: even- numbered blocks (0, 2, 4, 6, ..., 4,092, 4,094) 1 plane 1: odd- numbered blocks (1, 3, 5, 7, ..., 4,093, 4,095) plane 0: even- numbered blocks (4096, 4098, ..., 8,188, 8,190) plane 1: odd- numbered blocks (4,097,4,099, ..., 8,189, 8,191) 218 4,096 218 4,314 bytes 4,314 bytes 218 218 4,096 4,096 4,096 1 block 1 block 218 4,096 218 4,314 bytes 4,314 bytes 218 218 4,096 4,096 4,096 1 page = (4k + 218 bytes) 1 block = (4k + 218) bytes x 64 pages = (256k + 13k) bytes 1 plane = (256k + 13k) bytes x 2,048 blocks = 4,304mb 1 die = 4,304mb x 2 planes = 8,608mb 1 device = 8,608mb x 2 die = 17,216mb i/o0 i/o7 die 0 die 1 draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 17 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory bus operation micron confidential and proprietary advance bus operation the bus on the mt29fxxx devices is multip lexed. data i/o, addresses, and commands all share the same pins, i/o[7:0]. the 16gb and 32gb lga packaged devices each have two independent data i/o and command pads . these are i/o[7:0], ce#, we#, re#, cle, ale, wp#, and i/o[7-2:0-2], ce2#, we2#, re2#, cle2, ale2, wp2#. this provides inde- pendent data i/o, address, and command contro l for each half of a 16gb or 32gb device. the 64gb lga packaged device has two independent data i/o and command pads. these are i/o[7:0], ce#, ce3#, we#, re#, cle, ale, wp#, and i/o[7-2:0-2], ce2#, ce4#, we2#, re2#, cle2, ale2, wp2#. this provides independent data i/o, address, and com- mand control for each 16gb portion of the 64gb device. the command sequence normally consists of a command latch cycle, address input cycles, and one or more data cycles?either read or write. control signals ce#, we#, re#, cle, ale and wp# control nand flash device read and write opera- tions. on the 16gb, ce# and ce2# each control independent 8gb arrays. on the 32gb, ce# and ce2# each control independent 16gb arrays. ce2# functions the same as ce# for its own array; all operations described fo r ce# also apply to ce2#. on the 64gb, ce#, ce2#, ce3#, and ce4# each control independent 16gb arrays. ce2#, ce3#, and ce4# function the same as ce# for their own arra ys; all operations described for ce# also apply to ce2#, ce3#, and ce4#. ce# is used to enable the device. when ce# is low and the device is not in the busy state, the flash memory will accept co mmand, address, and data information. when the device is not performing an operat ion, the ce# pin is typically driven high and the device enters standby mode. the memory will enter standby if ce# goes high while data is being transferred and the device is not busy. this helps reduce power con- sumption. see figure 77 on page 100 and fi gure 85 on page 107 for examples of ce# ?don?t care? operations. the ce# ?don?t care? operation enables the nand flash to reside on the same asyn- chronous memory bus as other flash or sram devices. other devices on the memory bus can then be accessed while the nand flas h is busy with internal operations. this capability is important for designs that re quire multiple nand flash devices on the same bus. a high cle signal indicates that a command cycle is taking place. a high ale signal signifies that an address input cycle is occurring. commands commands are written to the command register on the rising edge of we# when: ? ce# and ale are low, and ?cle is high, and ? the device is not busy. as exceptions, the device accepts the read status, two-plane/multiple-die read status, and reset commands when busy. commands are transferred to the command register on the rising edge of we# (see figure 69 on page 96). commands are input on i/o[7:0]. draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 18 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory bus operation micron confidential and proprietary advance address input addresses are written to the address register on the rising edge of we# when: ? ce# and cle are low, and ?ale is high. addresses are input on i/o[7:0] only. bits no t part of the address space must be low. the number of address cycles required for each command varies. refer to the com- mand descriptions to determine addressing requirements. see tables 6?7, starting on page 22. data input data is written to the data register on the rising edge of we# when: ? ce#, cle, and ale are low, and ? the device is not busy. data is input on i/o[7:0]. see figure 71 on page 97 for additional data input details. read operations after a read command is issued, data is tran sferred from the memory array to the data register. r/b# goes low for t r and transitions high after the transfer is complete. when data is available in the data register, it is clocked out of the part by re# going low. see figure 76 on page 100 for detailed timing information. the read status (70h), or two-plane/multiple-die read status (78h) com- mand or the r/b# signal can be used to determine when the device is ready. if a controller is using a timing of 30ns or longer for t rc, use figure 72 on page 98 for proper timing. if t rc is less than 30ns, use figure 73 on page 98 for extended data output (edo) timing. ready/busy# the r/b# output provides a hardware meth od of indicating th e completion of pro- gram, erase, and read operations. the signal requires a pull-up resistor for proper operation. the signal is typically high, an d transitions to low after the appropriate command is written to the device. the signal pin?s open-drain driver enables multiple r/b# outputs to be or-tied. the read status command can be used in place of r/b#. typically r/b# would be connected to an in terrupt pin on the system controller (see figure 10 on page 19 ). on the 16gb mt29f16g08daa, r/b# provides a status indication for the 8gb section enabled by ce#, and r/b2# does the same fo r the 8gb section enabled by ce2#. r/b# and r/b2# can be tied together, or they can be used separately to provide independent indications for each 8gb section. on the 32gb mt29f32g08faa, r/b# provides a status indication for the 16gb section enabled by ce#, and r/b2# does the same for the 16gb section enabled by ce2#. r/b# and r/b2# can be tied together, or they can be used separately to provide independent indications for each 16gb section. on the 64gb device, r/b# provides a status indication for the 16gb section enabled by ce#; r/b2# provides a status indication for the 16gb section enabled by ce2#; r/b3# provides a status indication for the 16gb section enabled by ce3#; and r/b4# provides a draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 19 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory bus operation micron confidential and proprietary advance status indication for the 16gb enabled by ce4#. r/b#, r/b2#, r/b3#, and r/b4# can be tied together, or they can be used separately to provide independent indications for each 16gb section. rise time for the r/b# pin is determined by the combined capacitive loading of the r/b# circuit and rp. the actual value used for rp depends on the system timing requirements. large values of rp cause r/b# to be delayed si gnificantly. at the 10 to 90 percent points on the r/b# waveform, rise time is approximately two time constants (tc). time constants the fall time of the r/b# signal is determ ined mainly by the output impedance of the r/b# pin and the total load capacitance. refer to figures 11 and 12 on page 20 , which depict approximate rp values using a cir- cuit load of 100pf. the minimum value for rp is determined by th e output drive capability of the r/b# sig- nal, the output voltage swing, and v cc . figure 10: ready/busy# open drain tc r c = where r = rp (resistance of pull-up resistor), and c = total capacitive load. rp min () v cc max () v ol max () ? i ol i l + --------------------------------------------------------------- = 3.2 v 8 ma i l + --------------------------- = where i l is the sum of the input currents of all devices tied to the r/b# pin. rp r/b# open drain output v cc gnd device i ol draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 20 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory bus operation micron confidential and proprietary advance figure 11: t fall and t rise notes: 1. t fall and t rise are calculated at 10 percent?90 percent points. 2. t rise is primarily dependent on external pull -up resistor and extern al capacitive loading. 3. t fall 10ns at 3.3v. 4. see tc values in figure 13 for approximate rp value and tc. figure 12: i ol vs. rp figure 13: tc vs. rp 3.50 3.00 2.50 2.00 1.50 1.00 0.50 0.00 C1 0 2 4 0 2 4 6 t fall t rise vcc 3.3 tc v 3.50ma 3.00ma 2.50ma 2.00ma 1.50ma 1.00ma 0.50ma 0.00ma 0 2000 4000 6000 8000 10000 12000 i ol at 3.60v (max) rp i 1.20s 1.00s 800ns 600ns 400ns 200ns 0ns 02k 4k 6k 8k 10k 12k i ol at 3.60v (max) rc = tc c = 100pf rp t draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 21 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory bus operation micron confidential and proprietary advance notes: 1. wp# should be biased to cmos high or low for standby. 2. mode selection settings for this table: h = logic level high; l = logic level low; x = v ih or v il . table 5: mode selection cle ale ce# we# re# wp# mode hll hx read mode command input lhl hx address input hll hh write mode command input lhl hh address input lll hh data input lllh x sequential read and data output xxxhhx during read (busy) x xxxxh during program (busy) x xxxxh during erase (busy) x xxxxl write protect xxhxx0v/v cc 1 standby draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 22 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance command definitions notes: 1. indicates required data cycles between command cycle 1 and command cycle 2. 2. these commands are valid duri ng busy when an interleave d die operation is being per- formed. see ?interleaved die operations ? on page 67 for ad ditional details. 3. the sequential page read cache mode comma nd should not be issu ed prior to reading the last page of a block. 4. when using the random page read cache mode command, the plan e select bit must be the same as the page last read. 5. do not cross plane address boundaries when using read for internal data move and program for internal data move. see figu re 8 on page 15 for plane address bound- ary definitions. table 6: command set command command cycle 1 number of address cycles data cycles required 1 command cycle 2 valid during busy notes page read 00h 5 no 30h no 2 page read cache mode sequential 31h ? no ? no 3 page read cache mode random 00h 5 no 31h no 4 page read cache mode last 3fh ? no ? no read for internal data move 00h 5 no 35h no 2, 5 random data read 05h 2 no e0h no 2 read id 90h 1 no ? no read parameter page ech 1 no ? no read status 70h ? no ? yes program page 80h 5 yes 10h no 2 program page cache mode 80h 5 yes 15h no 2 program for internal data move 85h 5 optional 10h no 2, 5 random data input 85h 2 yes ? no 2 block erase 60h 3 no d0h no 2 reset ffh ? no ? yes 2 otp data program a0h 5 yes 10h no otp data protect a5h 5 no 10h no otp data read afh 5 no 30h no set features efh 1 4 ? no get features eeh 1 no ? no draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 23 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance notes: 1. do not cross plane address boundaries when using two-plane read for internal data move and two-plane program for internal data move. see figure 8 on page 15 for plane address boundary definitions. 2. the two-plane/multiple-die read status command must be used to check status dur- ing and following interleaved die operations. see ?inter leaved die operations? on page 67 for additional details. 3. the commands are valid during busy when interleaved die operations are being per- formed. see ?interleaved die operations ? on page 67 for ad ditional details. table 7: two-plane command set command command cycle 1 number of address cycles command cycle 2 number of address cycles command cycle 3 valid during busy notes two-plane page read 00h 5 00h 5 30h no two-plane read for internal data move 00h 5 00h 5 35h no 1 two-plane random data read 06h 5 e0h ? ? no two-plane/multiple-die read status 78h 3 ? ? ? yes 2, 3 two-plane program page 80h 5 11h-80h 5 10h no 3 two-plane program page cache mode 80h 5 11h-80h 5 15h no 3 two-plane program for internal data move 85h 5 11h-85h 5 10h no 1, 3 two-plane block erase 60h 3 d1h-60h 3 d0h no 3 draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 24 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance read operations page read 00h-30h to read a page from the nand flash array, write the 00h command to the command reg- ister, then write 5 address cycles, and conclude with the 30h command. to determine the progress of the data transfer from the nand flash array to the data register ( t r), monitor the r/b# signal; or alternately, issue a read status (70h) com- mand. if the read status command is used to monitor the data transfer, the user must re-issue the read (00h) command to receive data output from the data register. see figure 81 on page 104 and figure 82 on page 105 for examples. after the read com- mand has been re-issued, pulsing the re# line will result in outp utting data, starting from the initial column address. a serial page read sequence outputs a complete page of data. after 30h is written, the page data is transferred to the data regist er, and r/b# goes low during the transfer. when the transfer to the data register is complete, r/b# returns high. at this point, data can be read from the device. starting from the initial column address and going to the end of the page, read the data by repeatedly pulsing re# at up to the maximum t rc rate (see figure 14). for improved read operation performance use page read cache mode operations (see pages 34 through 36). figure 14: page read operation re# ce# ale cle i/ox 00h address (5 cycles) data output (serial access) 30h r/b# we# t r t wb don?t care draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 25 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance random data read 05h-e0h the random data read command enables the user to specify a new column address so the data at single or multiple addresses can be read. the random read mode is enabled after a normal page read (00h-30h) sequence. random data can be output after the initial page read by writing an 05h-e0h command sequence along with the new column address (2 cycles). the random data read command can be issued without limit within the page. only data on the current page can be read. pulsing the re# pin outputs data sequentially (see figure 15). the random data read command changes the column address of the die last addressed. figure 15: random data read operation read id 90h the read id command is used to read the 5 bytes of identifier codes programmed into the devices. the read id command reads a 5-byte table that includes manufacturer?s id, device configuration, and part-specific information. see table 9 on page 27, which shows complete listings of all configuration details. writing 90h to the command register puts the device into the read id mode. the com- mand register stays in this mode until another valid command is issued (see figure 16 ). figure 16: read id operation notes: 1. see table 9 on page 27 for byte definitions. re# i/ox 00h address (5 cycles) data output data output 30h 05h address (2 cycles) e0h r/b# t r w e# ce# ale cle re# i/ox address, 1 cycle 90h 00h or 20h byte 2 byte 0 1 byte 1 byte 3 byte 4 t ar t rea t whr draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 26 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance notes: 1. b = binary; h = hex. 2. the mt29f16g device id code reflects the configuration of each 8gb section. 3. the mt29f32g and mt29f64g de vice id code reflects the co nfiguration of each 16gb sec- tion. table 8: device id and configuration codes for address 00h options i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 value 1 notes byte 0 manufacturer id micron 001011002ch byte 1 device id mt29f8g08aaa 8gb, x8, 3v11010011d3h mt29f16g08[d/e]aa 16gb, x8, 3v 11010011d3h 2 mt29f32g08[f/g]aa 32gb, x8, 3v 11010101d5h3 mt29f64g08kaa 64gb, x8, 3v11010101d5h3 byte 2 number of die per ce 10000b 20101b cell type slc 0 0 00b number of simultaneously programmed pages 201 01b interleaved operations between multiple die not supported 0 0b supported 1 1b cache programming supported 1 1b byte value mt29f8g081001000090h mt29f16g081001000090h mt29f32g0811010001d1h mt29f64g0811010001d1h byte 3 page size 4kb 1 0 10b spare area size (bytes) 218b 1 1b block size (w/o spare) 256kb 1 0 10b organization x8 0 0b serial access (min) 20ns 0 1 0xxx1b byte value mt29fxxg08 001011102eh byte 4 reserved 0000b planes per ce# 2 01 01b 4 10 10b plane size 4gb 1 1 0 110b reserved 0 0b byte value mt29f8g08 0 110010064h mt29f16g08 0 110010064h mt29f32g08 0 110100068h mt29f64g080110100068h draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 27 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance notes: 1. h = hex. read parameter page ech the read parameter page function retrieves the data structure that describes the device's organization, featur es, timings, and other behavioral parameters. the data structure is repeated at least five times. figure 17 defines the read parameter page behavior. the random data read (05h-e0h) command is permitted during data output. figure 17: read parameter page (ech) byte values for read parameter page operations are provided in table 10 on page 28. when a range of bytes is defined in any row in the table, a number of values are also associated with that row. the lowest byte defined for a row correlates with the first hex value shown in the ?values? column of that row. unless otherwise stated, the hex values in table 10 are converted to decimal values to determine the actual timing for any given parameter. table 9: device id and configuration codes for address 20h address = 20h options i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 value notes byte 0 ?o? 010011114fh1 byte 1 ?n? 010011104eh byte 2 ?f? 0100011046h byte 3 ?i? 0100100149h byte 4 undefined xxxxxxxxxxh we# ale cle re# r/b# ech 00h t r p0 p1 ? p1022 p1023 i/o[7:0] draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 28 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance table 10: parameter page data structure byte description device values revision information and features block 0?3 parameter page signature byte 0: 4fh, ?o? byte 1: 4eh, ?n? byte 2: 46h, ?f? byte 3: 49h, ?i? ? 4fh, 4eh, 46h, 49h 4?5 revision number bit[15:2]: reserved (0) bit 1: 1 = supports onfi version 1.0 bit 0: reserved (0) ? 02h, 00h 6?7 features supported bit[15:5]: reserved (0) bit 4: 1 = supports odd to even page copyback bit 3: 1 = supports interleaved operations bit 2: 1 = supports nonsequential page programming bit 1: 1 = supports multiple logical unit (lun) operations bit 0: 1 = supports 16-bit data bus width mt29f8g08aaa 18h, 00h mt29f16g08daa 18h, 00h mt29f16g08eaa 18h, 00h mt29f32g08faa 1ah, 00h mt29f32g08gaa 1ah, 00h mt29f64g08kaa 1ah, 00h 8?9 optional commands supported bit[15:6]: reserved (0) bit 5: 1 = supports read unique id bit 4: 1 = supports internal data move bit 3: 1 = supports two-plane/multiple-die read status bit 2: 1 = supports get features and set features bit 1: 0 = does not support read cache commands bit 0: 1 = supports program page cache mode command ? 1dh, 00h 10?31 reserved (0) ? all 00h manufacturer information block 32?43 device manufacturer (12 ascii characters) ? 4dh, 49h, 43h, 52h, 4fh, 4eh, 20h, 20h, 20h, 20h, 20h, 20h draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 29 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance 44?63 device model (20 ascii characters) mt29f8g08aaa 4dh, 54h, 32h, 39h, 46h, 38h, 47h, 30h, 38h, 41h, 41h, 41h, 20h, 20h, 20h, 20h, 20h, 20h, 20h, 20h mt29f16g08daa 4dh, 54h, 32h, 39h, 46h, 31h, 36h, 47h, 30h, 38h, 44h, 41h, 41h, 20h, 20h, 20h, 20h, 20h, 20h, 20h mt29f16g08eaa 4dh, 54h, 32h, 39h, 46h, 31h, 36h, 47h, 30h, 38h, 45h, 41h, 41h, 20h, 20h, 20h, 20h, 20h, 20h, 20h mt29f32g08faa 4dh, 54h, 32h, 39h, 46h, 33h, 32h, 47h, 30h, 38h, 46h, 41h, 41h, 20h, 20h, 20h, 20h, 20h, 20h, 20h mt29f32g08gaa 4dh, 54h, 32h, 39h, 46h, 33h, 32h, 47h, 30h, 38h, 47h, 41h, 41h, 20h, 20h, 20h, 20h, 20h, 20h, 20h mt29f64g08kaa 4dh, 54h, 32h, 39h, 46h, 36h, 34h, 47h, 30h, 38h, 4bh, 41h, 41h, 20h, 20h, 20h, 20h, 20h, 20h, 20h 64 jedec manufacturer id ? 2ch 65?66 date code ? 00h, 00h 67?79 reserved (0) ? all 00h memory organization block 80?83 number of data bytes per page ? 00h, 10h, 00h, 00h 84?85 number of spare bytes per page ? dah, 00h 86?89 number of data bytes per partial page ? 00h, 02h, 00h, 00h 90?91 number of spare bytes per partial page ? 1bh, 00h 92?95 number of pages per block ? 40h, 00h, 00h, 00h 96?99 number of blocks per lun ? 00h, 10h, 00h, 00h 100 number of luns per ce# mt29f8g08aaa 01h mt29f16g08daa 01h mt29f16g08eaa 01h mt29f32g08faa 02h mt29f32g08gaa 02h mt29f64g08kaa 02h 101 number of address cycles bit[7:4]: column address cycles bit[3:0]: row address cycles ? 23h 102 number of bits per cell ? 01h 103?104 bad blocks maximum per lun ? 50h, 00h 105?106 the block endurance is reported in terms of a value and a multiplier according to th e following equation: value x 10 multiplier . byte 105 comprises the value. byte 106 comprises the multiplier. ? 01h, 05h table 10: parameter page data structure (continued) byte description device values draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 30 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance 107 guaranteed valid blocks at beginning of target ? 01h 108?109 block endurance for guaranteed valid blocks ? 00h, 00h 110 number of programs per page ? 04h 111 partial programming attributes bit[7:5]: reserved bit 4: 1 = partial page layout is partial page data followed by partial page spare bit[3:1]: reserved bit 0: 1 = partial page programming has constraints ? 00h 112 number of bits ecc correctability ? 01h 113 number of interleaved address bits bit[7:4]: reserved (0) bit[3:0]: number of interleaved address bits ? 01h 114 interleaved operation attributes bit[7:4]: reserved (0) bit 3: address restrict ions for program cache bit 2: 1 = program cache supported bit 1: 1 = no block address restrictions bit 0: overlapped/concurrent interleaving support ? 0eh 115?127 reserved (0) ? all 00h electrical parameters block 128 i/o pin capacitance mt29f8g08aaa 05h mt29f16g08daa 05h mt29f16g08eaa 05h mt29f32g08faa 0ah mt29f32g08gaa 0ah mt29f64g08kaa 0ah 129?130 timing mode support bit[15:6]: reserved (0) bit 5: 1 = supports timing mode 5 bit 4: 1 = supports timing mode 4 bit 3: 1 = supports timing mode 3 bit 2: 1 = supports timing mode 2 bit 1: 1 = supports timing mode 1 bit 0: 1 = supports timing mode 0, shall be 1 ? 3fh, 00h 131?132 program cache timing mode support bit[15:6]: reserved (0) bit 5: 1 = supports timing mode 5 bit 4: 1 = supports timing mode 4 bit 3: 1 = supports timing mode 3 bit 2: 1 = supports timing mode 2 bit 1: 1 = supports timing mode 1 bit 0: 1 = supports timing mode 0 ? 3fh, 00h 133?134 t prog maximum program page time (s) ? bch, 02h 135?136 t bers maximum block erase time (s) ? b8h, 0bh 137?138 t r maximum page read time (s) ? 19h, 00h 139?140 t ccs minimum change co lumn setup time (ns) ? 46h, 00h 141?163 reserved (0) ? all 00h vendor block table 10: parameter page data structure (continued) byte description device values draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 31 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance 164?165 vendor-specific revision number ? 01h, 00h 166 two-plane page read support bit[7:1]: reserved (0) bit 0: 1 = support for two-plane page read ? 01h 167 read cache support bit[7:1]: reserved (0) bit 0: 1 = support for read cache functions ? 01h 168 read unique id support bit[7:1]: reserved (0) bit 0: 1 = support for read unique id ? 01h 169 programmable i/o drive strength support bit[7:1]: reserved (0) bit 1: 1 = support for prog rammable i/o drive strength by ech command bit 0: 0 = no support for programmable i/o drive strength by b8h command ? 02h 170 number of programmable i/o drive strength settings bit[7:3]: reserved (0) bit[2:0] = number of programmable i/o drive strength settings ? 04h 171 programmable i/o drive strength feature address bit[7:0] = feature address used with programmable i/o drive strength by ech command ? 80h 172 programmable r/b# pull -down strength support bit[7:1]: reserved (0) bit 0: 1 = support programmable r/b# pull-down strength ? 01h 173 programmable r/b# pull-down strength feature address bit[7:0] = feature address used with programmable r/b# pull-down strength ? 81h 174 number of programmable r/b# pull-down strength settings bit[7:3]: reserved (0) bit [2:0] = number of pr ogrammable r/b# pull-down strength settings ? 04h 175 otp mode support bit[7:1]: reserved (0) bit 0: 1 = supports otp mode ? 01h 176 otp page start bit[7:0] = page where otp page space begins ? 02h 177 otp data protect address bit[7:0] = page address to use when issuing otp data protect command ? 01h 178 number of otp pages bit[15:4]: reserved (0) bit[3:0] = number of otp pages ? 0ah 179?253 ? all 00h table 10: parameter page data structure (continued) byte description device values draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 32 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance 254?255 integrity crc mt29f8g08aaa 3fh, 47h mt29f16g08daa e2h, 67h mt29f16g08eaa 6ch, 95h mt29f32g08faa c9h, 51h mt29f32g08gaa 47h, a3h mt29f64g08kaa 4dh, 88h redundant parameter pages 256?511 value of bytes 0?255 ? see bytes 0?255 512?767 value of bytes 0?255 ? see bytes 0?255 768?1,023 value of bytes 0?255 ? see bytes 0?255 1,024?1,279 value of bytes 0?255 ? see bytes 0?255 1,278?1,535 value of bytes 0?255 ? see bytes 0?255 1,536?1,791 value of bytes 0?255 ? see bytes 0?255 1,792?2,047 value of bytes 0?255 ? see bytes 0?255 2,048?2,303 value of bytes 0?255 ? see bytes 0?255 2,304?2,559 value of bytes 0?255 ? see bytes 0?255 2,560?2,815 value of bytes 0?255 ? see bytes 0?255 2,816?3,071 value of bytes 0?255 ? see bytes 0?255 3,072?3,327 value of bytes 0?255 ? see bytes 0?255 3,328?3,583 value of bytes 0?255 ? see bytes 0?255 3,584?4,095 value of bytes 0?255 ? see bytes 0?255 4,096?4,313 reserved (ffh) ? all ffh table 10: parameter page data structure (continued) byte description device values draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 33 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance read status 70h nand flash devices have an 8- bit status register that th e software can read during device operation. table 11 describes the status register. after a read status (70h) command, all read cycles are from the status register until a new command is given. changes in the status r egister are seen on i/o[7:0] as long as ce# and re# are low; it is not necessary to st art a new read cycle to see these changes. in devices that have more than one die sharing a common ce# pin, the read status (70h) command reports the status of the die th at was last addressed. during interleaved die operations, the two-plane/multiple-die read status (78h) command must be used to select the die that should report status. in this situation, using the read sta- tus (70h) command will result in bus contention, as both die will respond until the next operation is issued. while monitoring the status register to dete rmine when the transfer from the flash array to the data register ( t r) is complete, the user must re -issue the read (00h) command to make the change from status to data. after the read command has been re-issued, pulsing the re# line will result in outputti ng data, starting from the initial column address. notes: 1. status register bit 0 reports a ?1? if a two-plane program or two-plane block erase operation fails on one or both planes. status register bit 1 reports a ?1? if a two-plane program page cache mode operation fa ils on one or both planes. use two- plane/multiple-die read status (78h) to de termine the plane on which the operation failed. 2. status register bit 5 is ?0? during the actual pr ogramming operation. if cache mode is used, this bit will be ?1? when al l internal operatio ns are complete. 3. status register bit 6 is ?1? wh en the cache is ready to accept new data. r/b# follows bit 6 (see figure 19 on page 36 and figure 22 on page 39). 4. status register bit 7 typically mirrors the st atus of the wp# pin. however, when the otp program data command is used, status register bit 7 returns ?0? if the otp area is pro- tected. this bit is not modified until the next program or erase command is issued. table 11: status register bit definition sr bit program page program page cache mode page read page read cache mode block erase definition 0 1 pass/fail pass/fail (n) ? ? pass/fail 0 = successful program/erase 1 = error in program/erase 1 ? pass/fail (n -1) ? ? ? 0 = successful program 1 = error in program 2? ? ? ? ? 0 3? ? ? ? ? 0 4? ? ? ? ? 0 5 ready/busy ready/busy 2 ready/busy ready/busy 2 ready/busy 0 = busy 1 = ready 6 ready/busy ready/busy cache 3 ready/busy ready/busy cache 3 ready/busy 0 = busy 1 = ready 7 4 write protect write protect write pr otect write protect write protect 0 = protected 1 = not protected draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 34 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance figure 18: status register operation for read status page read cache mode operations micron nand flash devices have a cache register that can be used to increase read operation speed. data can be output from the device's cache register while concurrently moving a page from the nand flash array to the data register. to begin a page read cache mode sequence, begin by reading a page from the nand flash array to the cache register using the page read (00h-30h) command (see ?page read 00h-30h? on page 24). r/b# goes low during t r (status register bits 6 and 5 = 00). after t r (r/b# is high and status register bits 6 and 5 = 11), issue either of these commands: ? page read cache mode sequential (31h) command to begin copying the next sequential page from the nand flash array to the data register ? page read cache mode random (00h-31h) command to begin copying the page specified in this command from the nand flash array to the data register. after the page read cache mode sequential or page read cache mode ran- dom command has been issued, r/b# goes low (status register bits 6 and 5 = 00) for t dcbsyr1 while the next page begins copying into the data register. after t dcbsyr1, r/b# goes high and status register bits 6 an d 5 = 10, indicating that the cache register is available and that a page is being copied from the nand flash array to the data register. at this point data can be output from the cache register, beginning at column address 0, by toggling re#. the random data read (05h-e0h) command can be used to change the column address of the data being output by the device. after outputting the desired number of bytes from the cache register, it is possible to either begin an additional page read ca che mode (31h or 00h-31h) operation or issue the page read cache mode last (3fh) command. if an additional page read cache mode ( 31h or 00h-31h) command is issued, r/b# goes low (status register bits 6 and 5 = 00) for t dcbsyr2 while the data register is cop- ied to the cache register, then the next page begins copying into the data register. after t dcbsyr2, r/b# goes high and status regist er bits 6 and 5 = 10, indicating that the cache register is available and that the specified page is copying from the nand flash array to the data register. at this point data can be output from the cache register, begin- ning at column address 0, by toggling re#. the random data read (05h-e0h) com- mand can be used to change the column addr ess of the data being output by the device. if the page read cache mode last (3fh) command is issued, r/b# goes low (status register bits 6 and 5 = 00) for t dcbsyr2 while the data register is copied into the cache register. after t dcbsyr2, r/b# goes high and status re gister bits 6 and 5 = 11, indicating that the cache register is available and that the nand flash array is ready. at this point 70h ce# cle we# re# i/ox status output t rea t clr draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 35 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance data can be output from the cache register, beginning at column address 0, by toggling re#. the random data read (05h-e0h) command can be used to change the column address of the data being output by the device. during device busy times, t dcbsyr1 and t dcbsyr2, the only valid commands are read status (70h, 78h) and reset (ffh). unti l status register bit 5 = 1, the only valid commands during page read cache mode operations are read status (70h, 78h), read (00h), page read cache mode (31h and 00h-31h), random data read (05h- e0h), and reset (ffh). page read cache mode sequential 31h the page read cache mode sequential (31h) command reads the next sequential page within a block into the data register wh ile the previous page is output from the cache register. to issue this command, write 31h to the command register. after this command is issued, r/b# goes low (s tatus register bits 6 and 5 = 00) for either t dcbsyr1 or t dcbsyr2. after t dcbsyr1 or t dcbsyr2, r/b# goes high and status reg- ister bits 6 and 5 = 10 to indicate that the cach e register is available and that the specified page is copying from the nand flash array to th e data register. at this point data can be output from the cache register by toggling re# beginning at column address 0. the ran- dom data read (05h-e0h) command can be us ed to change the column address of the data being output by the device. do not issue the 31h command after reading the last page of the block into the data reg- ister. instead, issue the 3fh command. crossing block boundaries with the page read cache mode sequential (31h) command is prohibited. page read cache mode random 00h-31h the page read cache mode random (00h-31h) command reads the specified page into the data register while the previous page is output from the cache register. to issue this command, write 00h to the command regi ster, then write 5 address cycles to the address register. conclude the sequence by writing 31h to the command register. the column address in the address specified is ignored. after this command is issued, r/b# goes low (s tatus register bits 6 and 5 = 00) for either t dcbsyr1 or t dcbsyr2. after t dcbsyr1 or t dcbsyr2, r/b# goes high and status reg- ister bits 6 and 5 = 10 to indicate that the cach e register is available and that the specified page is copying from the nand flash array to th e data register. at this point data can be output from the cache register, beginning at column address 0, by toggling re#. the random data read (05h-e0h) command can be used to change the column address of the data being output by the device. do not issue the 00h-31h command to a differe nt plane than the previously read page? the plane-select bit must be set to the same value. if crossing plane boundaries is required, complete the page read cache mode operation using the 3fh command, then start a page read (00h-30h) operation to the new plane. page read cache mode last 3fh the page read cache mode last (3fh) command copies a page from the data regis- ter to the cache register without beginning a new page read cache mode operation. to issue the page read cache mode last command, write 3fh to the command reg- ister. draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 36 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance after this command is issued, r/b# goes lo w (status register bits 6 and 5 = 00) for t dcbsyr2. after t dcbsyr2, r/b# goes high and status re gister bits 6 and 5 = 11 to indi- cate that the cache register is available and that the nand flash array is ready. at this point data can be output from the cache register, beginning at column address 0, by tog- gling re#. the random data read (05h-e0h) command can be used to change the column address of the data being output by the device. figure 19: page read cache mode operation re# ce# ale i/ox 00h address (5 cycles) data output 31h 30h r/b# w e# t r t wb t dcbsyr1 re# ce# ale cle i/ox r/b# w e# t dcbsyr2 t dcbsyr2 data output 3fh data output address (5 cycles) 00h 31h 1 1 sequential page read cache mode operation random page read cache mode operation draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 37 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance program operations program page 80h-10h micron nand flash devices are inherently page-programmed devices. pages must be programmed consecutively within a block, the from the least significant page address to the most significant page address (that is, 0, 1, 2, ?63). random page address program- ming is prohibited. micron slc nand flash devices support pa rtial-page programming operations. this means that any single bit can only be programmed one time before an erase is required; however, the page can be partitioned such that a maximum of four programming opera- tions are allowed before an erase is required. serial data input 80h program page operations require loading the serial data input (80h) command into the command register, followed by 5 addr ess cycles, then the data. serial data is loaded on consecutive we# cycles starting at the given address. the program (10h) command is written after the data input is complete. the control logic automatically executes the proper algorithm and controls all the necessary timing to program and ver- ify the operation. write verification only detects ?1s? that are not successfully written to ?0s.? r/b# goes low for the duration of array programming time, t prog. the read status (70h) command and the reset (ffh) command are the only commands valid during the programming operation.) bit 6 of the status register will reflect the state of r/b#. when the device reaches ready, read bit 0 of the status register to determ ine if the program operation passed or failed (see figure 20). the command register stays in read status register mode until another valid command is written to it. random data input 85h after the initial data set is input, additional data can be written to a new column address with the random data input (85h) command. the random data input com- mand can be used any number of times in the same page prior to issuing the page write (10h) command. see figure 21 on page 38 for the proper command sequence. figure 20: program and read status operation notes: 1. command can be 70h or 78h. i/ox 80h address (5 cycles) 10h 70h 1 r/b# t prog status i/o 0 = 0 program successful i/o 0 = 1 program error d in draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 38 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance figure 21: random data input program page cache mode 80h-15h cache programming is actually a buffered programming mode of the standard pro- gram page command. programming is started by loading the serial data input (80h) command to the command register, followed by 5 cycles of address, and a full or partial page of data. the data is initially copied into the cache register, and the cache program (15h) command is then latched to the command register. data is transferred from the cache register to the data register on the rising edge of we#. r/b# goes low during this transfer time. after the data has been copied into the data register and r/b# returns to high, memory array programming begins. when r/b# returns to high, new data can be written to the cache register by issuing another cache program command sequence. th e time that r/b# stays low will be controlled by the actual programming time. the first time through equals the time it takes to transfer the cache register contents to the data register. on the second and sub- sequent programming passes, transfer from the ca che register to the data register is held off until current data register content has been programmed into the array. the program page cache mode command can cross block boundaries. if a pro- gram page cache mode operation crosses die boundaries, handle as described in ?interleaved program page cache mode operations? on page 71. random data input commands are allowed during program page cache mode operations. bit 6 (cache r/b#) of the status register can be read by issuing the read status (70h or 78h) commands to determine when the cache re gister is ready to accept new data. the r/b# pin always follows bit 6. bit 5 (r/b#) of the status register can be polled to determine when the actual program- ming of the array is complete for the current programming cycle. if just the r/b# pin is used to determine programming completion, the last page of the program sequence must use the program page (10h) command instead of the cache program (15h) command. if the cache program (15h) command is used every time, including the last page of the programmi ng sequence, status register bit 5 must be used to determine when programming is complete (see figure 22 on page 39). bit 1 of the status register returns the pass/f ail for the previous page when bit 6 of the status register is a ?1? (ready state). the pass/fail status of the current program opera- tion is returned with bit 0 of the status regist er when bit 5 of the status register is a ?1? (ready state) (see figure 22 on page 39). i/ox 80h address (5 cycles) 85h address (2 cycles) 10h 70h 1 r/b# t prog d in d in status draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 39 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance figure 22: program page cache mode example notes: 1. command can be 70h or 78h. check i/o[6:5] fo r internal ready/busy. ch eck i/o[1:0] for pass fail. re# can stay low or pulse multip le times after a 70h or 78h command. internal data move an internal data move requires two comm and sequences. issue a read for internal data move (00h-35h) command first, then the program for internal data move (85h-10h) command. data moves are only suppo rted within the plane from which data is read. read for internal data move 00h-35h the read for internal data move (00h-35h) command is used in conjunction with the program for internal data move (85h-10h) command. first, 00h is written to the command register, then the internal source address is written (5 cycles). after the address is input, the read for internal data move (35h) command writes to the command register. this transfers a page from memory into the cache register. all 5 address cycles are required when a read for internal data move command is issued. after a read for internal data move (00h-35h) command is issued and r/b# returns high, signifying operation completio n, the data transferred from the source page into the cache register may be read out by toggling re#. data is output sequentially from the column address originally specified with the read for internal data move (00h-35h) command. random data read (05h-e0h) commands can be issued without limit after the read for internal data move command. the memory device is now ready to accept the program for internal data move command. refer to the description of this command in the following section. t cbsy r/b# i/ox r/b# i/ox address & data input 80h 15h 80h 15h 80h 15h 80h 10h t lprog 1 80h 15h 80h 10h status output 2 status output 2 70h t prog 70h a: without status reads b: with status reads address & data input address & data input address & data input address & data input address & data input t cbsy t cbsy t cbsy draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 40 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance program for internal data move 85h-10h after the read for internal data move (00h-35h) command has been issued and r/b# goes high, the program for internal data move (85h-10h) command can be written to the command register. this command transfers the data from the cache register to the data register and programmi ng of the new destination page begins. the sequence: 85h, destination address (5 cycles), then 10h, is written to the device. after 10h is written, r/b# goes low while the control logic automatically programs the new page. the read status command and bit 6 of the st atus register can be used instead of the r/b# line to determine when the write is comple te. bit 0 of the status register indicates if the operation was successful. the random data input (85h) command can be used during the program for internal data move command sequence to modify a word or multiple words of the original data. first, data is copied into the cache register using the 00h-35h command sequence, then the random data input (8 5h) command is written along with the address of the data to be modified next. new da ta is input on the external data pins. this copies the new data into the cache register. when 10h is written to the command register, the original data plus the modified data is transferred to the data register, and progra mming of the new page is started. the ran- dom data input command can be issued as many times as necessary before starting the programming sequence with 10h (see figures 23 and 24 on page 41). because internal data move operations do not use external memory, ecc cannot be used to check for errors before programming the data to a new page. this can lead to a data error if the source page contains a bit error due to charge loss or charge gain. in the case that multiple internal data mo ve operations are performed, these bit errors may accumulate without correction. for this reason, it is highly recommended that systems using internal data move operations also use a robust ecc scheme that exceeds the minimum required ecc. draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 41 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance figure 23: internal data move notes: 1. command can be 70h or 78h. figure 24: internal data move with optional data output and random data input notes: 1. command can be 70h or 78h. optional r/b# re# we# i/ox t r t prog data output status address (5 cycles) 85h 10h unlimited number of repetitions 70h 1 address (5 cycles) address (2 cycles) data output 35h (or 30h) 05h e0h 00h optional t r address (2 cycles) status data 10h 85h 85h t prog unlimited number of repetitions 70h 1 00h address (5 cycles) address (5 cycles) data output 35h (or 30h) r/b# i/ox draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 42 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance block erase operation block erase 60h - d0h erasing occurs at the block level. for ex ample, the mt29f8g08axa device has 4,096 erase blocks, organized into 64 pages per bl ock, 4,314 bytes per page (4,096 + 218 bytes). each block is 269k bytes (2 56k + 13k bytes). the block erase command operates on one block at a time (see figure 25). the last 3 cycles of addresses of the 5-cycle addressing sequence are required for a block erase operation. the first 2 cycles of addresses must not be used. although the page address bits are loaded, they are a ?don?t care? and are ignored for block erase operations, since these bits normally specify the page address within a block. see ?addressing? on page 13 for details. the actual command sequence is a two-st ep process. the erase setup (60h) com- mand is first written to the command register . then 3 cycles of addresses are written to the device. next, the erase confirm (d0h) command is written to the command reg- ister. at the rising edge of we#, r/b# goes low and the control logic automatically con- trols the timing and erase-verify oper ations. r/b# stays low for the entire t bers erase time. the read status (70h and 78h) commands can be used to check the status of the error. when bit 6 is ?1,? the erase operation is complete. bit 0 indicates a pass/fail condition where ?0? is pass (see figure 25, and table 11 on page 33). figure 25: block erase operation notes: 1. command can be 70h or 78h. re# ce# ale cle i/ox 60h address input (3 cycles) status d0h 70h 1 r/b# we# t bers don?t care i/o 0 = 0 erase successful i/o 0 = 1 erase error draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 43 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance one-time programmable (otp) area this micron nand flash device offers a protected, one-time programmable nand flash memory area. ten full pages (4,314 bytes) of otp data is available on the device, and the entire range is guaranteed to be good. the otp area is accessible only through the otp commands. customers can use the otp area in any way they desire; typical uses include programming serial numbers or other data for permanent storage. in micron nand flash devices, the otp area le aves the factory in a non-written state (all bits are ?1s?). programming enables the user to program only ?0? bits in the otp area. the otp area cannot be erased, even if it is not protected. protecting the otp area sim- ply prevents further programming of the otp area. while the otp area is referred to as ?one-time programmable,? micron provides a unique way to program and verify data?bef ore permanently protecting it and prevent- ing future changes. otp programming and protection are accompli shed in two discrete operations. first, using the otp data program (a0h-10h) command, an otp page is programmed entirely in one operation. programming can occur on other pages within the otp area in a similar manner. second, the otp area is permanently protected from further program- ming using the otp data protect (a5h-10h) command. the pages within the otp area can always be read using the otp data read (afh-30h) command, whether or not it is protected. to determine whether or not the device is bu sy during an otp operation, either monitor r/b# or use the read status (70h) command. use of the two-plane/multiple-die read status (78h) command is prohibited during and following otp operations. otp data program a0h-10h the otp data program (a0h-10h) command is used to write data to the pages within the otp area. an entire page is programmed at one time. there is no erase operation for the otp pages. otp data program enables programming into an offset of an otp page, using the two bytes of column address (ca[12:0]). the command is compatible with the random data input (85h) command. the otp data program command will not execute if the otp area has been protected. to use the otp data program command, issue the a0h command. issue 5 address cycles: the first 2 address cycles are the column address, and for the remaining 3 cycles select a page in the range of 02h-00h-00h through 0bh-00h-00h. next, write from 1 to 4,314 bytes of data. after data input is complete, issue the 10h command. the internal control logic automatically executes the pr oper programming algorithm and controls the necessary timing for programming and verification. program verification only detects ?1s? that are not successfully written to ?0s.? r/b# goes low during the duration of the array programming time ( t prog). the read status (70h) command is the only comma nd valid during the otp data program operation. bit 5 of the status register will reflect the state of r/b#. when the device is ready, read bit 0 of the status register to determine if the operation passed or failed (see table 11 on page 33). it is possible to program each otp page a maximum of one time. the otp data program command also accepts the random data input (85h) command (see figure 27 on page 45). draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 44 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance if an otp data program command is issued after the otp area has been protected, r/b# will go low for t obsy. figure 26: otp data program notes: 1. the otp page must be within the range 02h?0bh. we# ce# ale cle re# r/b# i/ox don?t care otp data written (following "good" status confirmation) t wc t wb t prog otp data input command program command read status command 1 up to m bytes serial input x8 device: m = 4,314 bytes a0h col add 1 col add 2 d in n d in m 00h 00h 10h 70h status otp page 1 draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 45 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance figure 27: otp program with random data input notes: 1. the otp page must be within the range 02h?0bh. we# ce# ale cle re# r/b# i/ox don?t care otp data written (following "good" status confirmation) t wc t wb t prog otp data input command program command read status command 1 up to m bytes serial input a0h col add 1 col add 2 d in n d in m 00h 00h 70h status otp page 1 random data input command new column address in selected otp page 85h col add 1 d in p col add 2 10h d in q x8 device: m = 4,314 bytes draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 46 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance otp data protect a5h-10h the otp data protect (a5h-10h) command is used to protect all the data in the otp area. after the data is protected it cannot be programmed further. when the otp area is protected, the pages within the area are no longer programmable and cannot be unpro- tected. to use the otp data protect command, issue the a5h command. next, issue the fol- lowing 5 address cycles: 00h-00h-01h-00h-00h. finally, issue the 10h command. if an otp data program command is issued after the otp area has been protected, r/b# will go low for t dbsy. the read status (70h) command is the on ly command valid during the otp data protect operation. bit 5 of the status register will reflect the state of r/b#. when the device is ready, read bit 0 of the status register to determine if the operation passed or failed (see table 11 on page 33). figure 28: otp data protect notes: 1. otp data is protected foll owing ?good? status confirmation. w e# ce# ale cle re# r/b# i/ox don?t care t wc t wb t prog otp data protect command otp data protected 1 program command read status command a5h col 00h col 00h 10h 70h status 01h 00h 00h draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 47 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance otp data read afh-30h the otp data read (afh-30h) command is used to read data from a page within the otp area. an otp page within the otp area is available for reading data whether or not the area is protected. to use the otp data read command, issue the afh command. next, issue 5 address cycles: the first 2 address cycles are the column address, and for the remaining 3 cycles select a page in the range of 02h-00h-00h through 0bh-00h-00h. finally, issue the 30h command. r/b# goes low ( t r) while the data is moved from the otp page to the data register. the read status (70h) command and the reset (ffh) command are the only commands valid during the otp data read operation. bi t 5 of the status register will reflect the state of r/b#. for details, refer to table 11 on page 33. normal read operation timings apply to otp read accesses (see figure 29). additional pages within the otp area can be selected by repeating the otp data read command. the otp data read command is compatible with the random data output (05h- e0h) command. figure 29: otp data read operation notes: 1. the otp page must be within the range 02h?0bh. we# ce# ale cle re# r/b# i/ox busy t r afh 00h 00h 30h don?t care otp page 1 col add 2 col add 1 d out n d out n d out n + 1 draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 48 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance figure 30: otp data read with random data read notes: 1. the otp page must be within the range 02h?0bh. we# ce# ale cle re# r/b# i/ox busy t r d out n d out n + 1 d out m afh 00h 00h 30h col add 1 col add 2 don?t care otp page 1 05h col add 1 d out h d out p col add 2 e0h draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 49 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance features operations the get features (eeh) and set features (efh) commands are used to alter nand flash device default power-on behaviors. these commands use a one-byte feature address to determine which subfeature parameters are to be read or modified. each fea- ture address (in the range of 00h to ffh) is defined in table 12. the get features com- mand reads the subfeature parameters (p1?p4 ) at the specified feature address. the set features (efh) command places subfeature parameters (p1?p4) at the specified fea- ture address. get features eeh the get features command is used to return the current subfeature parameters (see table 13 on page 50) at the specified feature address. figure 31 on page 51 defines get features behavior and timing. r/b# goes low ( t feat) while the subfeature parameters are being loaded from the specified feature address. the read status (70h) command and the reset (ffh) com- mand are the only commands available during get features operation. bits 5 and 6 of the status register will reflect the state of r/b#. table 12: features table feature address definition 00h reserved 01h timing mode 02h?7fh reserved 80h programmable i/o drive strength 81h programmable r/b# pull-down strength 82h-ffh reserved draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 50 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance notes: 1. the timing-mode feature address is used to change the default ti ming mode. the timing mode should be selected to indicate the maximum speed at which the device will receive commands, addresses, and data cycles. the five supported settings fo r the timing mode are shown. the default timing mode is mode 0. the device returns to mode 0 when the device is power cycled. supported timing mode s are reported in the parameter page. notes: 1. the programmable drive strength featur e address is used to change the default i/o drive strength. drive strength should be sele cted based on expected loading of the mem- ory bus. this table shows the four supported output drive-st rength settings. the default drive strength is full strength. the device re turns to the default drive strength mode when the device is power cycled. ac timing parameters may need to be relaxed if i/o drive strength is not set to full. table 13: feature address 01h: timing mode subfeature parameter options i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 value notes p1 timing mode mode 0 (default) reserved (0) 0 0 0 00h 1 mode 1 reserved (0) 0 0 1 01h mode 2 reserved (0) 0 1 0 02h mode 3 reserved (0) 0 1 1 03h mode 4 reserved (0) 1 0 0 04h mode 5 reserved (0) 1 0 1 05h p2 reserved (0) 00h p3 reserved (0) 00h p4 reserved (0) 00h table 14: feature address 80h: programmable i/o drive strength subfeature parameter options i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 value notes p1 i/o drive strength full (default) reserved (0) 0 0 00h 1 three-quarters reserved (0) 0 1 01h one-half reserved (0) 1 0 02h one-quarter reserved (0) 1 1 03h p2 reserved reserved (0) 00h p3 reserved reserved (0) 00h p4 reserved reserved (0) 00h draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 51 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance notes: 1. the programmable r/b# pull-down strength feature address is used to change the default r/b# pull-down strength. r/b# pull-down stren gth should be selected based on expected loading of r/b#. the four supported pull-down strength settings are shown. the default pull-down strength is full strength. the devi ce returns to the defa ult pull-down strength when the device is power cycled. figure 31: get features operation notes: 1. p1?p4 are the subfeature parameters to be read from the specified feature address (fa). table 15: feature address 81h: programmable r/b# pull-down strength subfeature parameter options i/o7 i/o6 i/o5 i/o4 i/o3 i/o2 i/o1 i/o0 value notes p1 r/b# pull-down strength full (default) reserved (0) 0 0 00h 1 three-quarters reserved (0) 0 1 01h one-half reserved (0) 1 0 02h one-quarter reserved (0) 1 1 03h p2 reserved reserved (0) 00h p3 reserved reserved (0) 00h p4 reserved reserved (0) 00h we# ce# ale cle re# i/ox feature address, 1 cycle eeh fa p3 p1 1 p2 p4 t feat r/b# draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 52 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance set features efh the set features command is used to set the subfeature parameters at a specified feature address. these parameters are stored in the device until the device is powered down. the subfeature parameters are applied to all die on the ce# to which this com- mand is issued. figure 32 depicts set features behavior and timing. after all four subfeature parameters, p1?p4, are issued, r/b# goes low for t feat while the subfeature parameters are written to the specified feature address. the read sta- tus (70h) command and the reset (ffh) co mmand are the only valid commands dur- ing set features operation. bits 5 and 6 of th e status register will reflect the state of r/b#. figure 32: set features operation notes: 1. p1?p4 are the subfeature parameters to be written to the specified feature address (fa). we# ce# ale cle re# i/ox feature address, 1 cycle efh t adl p3 p2 p4 t feat r/b# fa p1 1 draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 53 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance two-plane operations this nand flash device is divided into tw o physical planes. each plane contains a 4,314-byte data register, a 4,314-byte cache register, and a 2,048-block flash array. two- plane commands make better us e of the flash arrays on these physical planes by per- forming program, read, or erase operations simultaneously, significantly improving system performance. two-plane addressing two-plane commands require two addresse s, one address per plane. these two addresses are subject to the following requirements: ? the least significant block address bit, ba6, must be different for both addresses. ? the most significant block address bit, ba18 for 32gb and 64gb devices, must be identical for both addresses. ? the page address bits, pa[5:0], must be identical for both addresses. two-plane page read 00h-00h-30h the two-plane page read (00h-00h-30h) operation is similar to the page read (00h-30h) operation. it transfers two pages of data from the flash array to the data regis- ters. each page must be from a different plane on the same die. to enter the two-plane page read mode, write the 00h command to the command register, then write 5 address cycles for pl ane 0 (ba6 = ?0?). next, write the 00h com- mand to the command register, then write 5 address cycles for plane 1 (ba6 = ?1?). finally, issue the 30h command. the first-pl ane and second-plane addresses must meet the two-plane addressing requirements, and, in addition, they must have identical col- umn addresses. after the 30h command is written, page data is transferred from both planes to their respective data registers in tr. during thes e transfers, r/b# goes low. when the trans- fers are complete, r/b# returns high. to read out the data from the plane 0 data regis- ter, pulse re# repeatedly. after the data cycle from the plane 0 address completes, issue a two-plane random data read (06h-e0h) command to select the plane 1 address, then repeatedly pulse re# to read out th e data from the plane 1 data register. alternatively, the read status (70h) command can monitor the data transfers. when the transfers are complete, status register bit 6 is set to ?1.? to read data from one of the two planes, the user must first issue th e two-plane random data read (06h-e0h) command followed by 5 address cycles (see ?two-plane random data read 06h- e0h? on page 54). to read out data from th e plane and column address specified with the two-plane random data read command, pulse re# repeatedly. when the data cycle is complete, issue a two-plane random data read (06h-e0h) command to select the other plane. to output the data beginning at the specified column address, pulse re# repeatedly. use of the two-plane/multiple-die read status (78h) command is supported during and following a two-plane page read operation. the same die to which the two-plane page read command was issued must remain selected when data is read out from the nand flash device. otherwise, the data read out will be invalid data for the two-plane page read command issued. a die can be selected by issuing a two- plane/multiple-die read st atus (78h) command to any valid address location on a die. draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 54 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance two-plane random data read 06h-e0h the two-plane random data read (06h-e0h) command selects a plane and col- umn address from which to read data af ter a two-plane page read (00h-00h-30h) command. to issue a two-plane random data read command, issue the 06h command, then 5 address cycles, and follow with the e0h command. pulse re# repeatedly to read data from the new plane beginning at the specified column address. the primary purpose of the two-plane rand om data read command is to select a new plane and column address within that pl ane. if a new plane does not need to be selected, then it is possible to use the random data read (05h-e0h) command instead (see ?random data read 05h-e0h? on page 25). draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 55 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance figure 33: two-plane page read notes: 1. column and page addresses must be the same. 2. the least-significant block address bit, ba6, must not be the same for the first- and second-plane addresses. cle we# ale re# i/ox r/b# cle we# ale re# i/ox r/b# 00h column add 1 column add 2 row add 1 row add 2 row add 3 column add 1 column add 2 row add 1 row add 2 row add 3 column add 1 column add 2 row add 1 row add 2 row add 3 00h 30h d out 0d out 1d out 06h e0h d out 0d out 1d out t r plane 0 address column address j plane 1 address plane 1 address plane 0 data plane 1 data page address m page address m 1 1 column address j draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 56 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance figure 34: two-plane page read with random data read r/b# re# i/ox r/b# re# i/ox 00h 00h address (5 cycles) 05h e0h 30h t r plane 0 address plane 0 data plane 0 data address (5 cycles) address (2 cycles) data output data output plane 1 address 06h 05h e0h e0h plane 1 data plane 1 data address (5 cycles) address (2 cycles) data output data output plane 1 address 1 1 draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 57 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance two-plane program page 80h-11h-80h-10h the two-plane program page (80h-11h-80h-10h) operation is similar to the pro- gram page (80h-10h) operation. it programs two pages of data from the data registers to the flash arrays. the pages must be programmed to different planes on the same die. within a block, the pages must be programmed consecutively from the least significant to most significant page address. random page programming within a block is prohib- ited. the first-plane address and the second -plane address must meet the two-plane addressing requirements (see ?two-plane addressing? on page 53). to begin the two-plane program page op eration, write the 80h command to the command register; write 5 address cycles for th e first plane; then write the data. serial data is loaded on consecutive we# cycles starting at the given address. next, write the 11h command. the 11h command is a ?dummy? command that informs the control logic that the first set of data for the firs t plane is complete. no programming of the nand flash array occurs. r/b# goes low for t dbsy, then returns high. the read status (70h) command also indicate s that the device is ready when status register bit 6 is set to ?1.? the only valid commands during t dbsy are read status (70h and 78h) and reset (ffh). after t dbsy, write the 80h command to the comma nd register; write 5 address cycles for the second plane; then write the data. the program (10h) command is written after the second-plane data input is complete. after the 10h command is written, the contro l logic automatically executes the proper algorithm and controls all the necessary timing to program and verify the operations to both planes. write verification only detect s ?1s? that are not successfully written to ?0s.? r/b# goes low for the duration of the array programming time (tprog). when pro- gramming and verification are complete, r/b# returns high. the read status (70h) command also indicates that the device is read y when status register bit 6 is set to ?1.? the only valid commands during t prog are read status (70h, 78h) and reset (ffh). if the read status (70h) command indicates an error in the operation (status register bit 0 is ?1?), use the two-plane/mult iple-die read status (78h) command twice?once for each plane?to determine which plane operation failed. during serial data input for either plan e, the random data input (85h) command can be used any number of times to change the column address within that plane. for details on this command, see ?random data input 85h? on page 37. figure 35 on page 57 shows two-plane program page operation. figure 35: two-plane program page notes: 1. command can be 70h or 78h. r/b# i/ox 80h address (5 cycles) 70h 1 10h 11h 80h t dbsy t prog 1st-plane address address (5 cycles) data input data input status 2nd-plane address draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 58 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance figure 36: two-plane program page with random data input two-plane program page cache mode 80h-11h-80h-15h the two-plane program page cache mode (80h-11h-80h-15h) operation is simi- lar to the program page cache mode (80h-15h) operation. it cache programs two pages of data from the data registers to th e nand flash arrays. the pages must be pro- grammed to different planes on the same di e. within a block, the pages must be pro- grammed consecutively from the least significant to the most significant page address. random page programming within a block is prohibited. the first-plane and second- plane address must meet the two-plane addressing requirements (see ?two-plane addressing? on page 53). to enter the two-plane program page cache mode, write the 80h command to the command register, write 5 address cycles for the first plane, then write the data. serial data is loaded on consecutive we# cycles, starting at the given address. next, write the 11h command. the 11h command is a ?dummy? command that informs the control logic that the first set of data for the firs t plane is complete. no programming of the nand flash array occurs. r/b# goes low for t dbsy, then returns high. the read sta- tus command also indicates that the device is ready when status register bit 6 is set to ?1.? the program page cache mode command ca n cross block boundaries; it cannot cross die boundaries. the only valid commands during t dbsy are read status (70h and 78h) and reset (ffh). after t dbsy, write the 80h command to the comma nd register, write 5 address cycles for the second plane, then write the data. the cache write (15h) command is written after the second-plane data input is complete . data is transferred from the cache regis- r/b# i/ox r/b# i/ox 80h address (5 cycles) 11h 80h 85h t dbsy t prog 1st-plane address address (2 cycles) data input address (5 cycles) 2nd-plane address data input data input 85h 10h address (2 cycles) 1 1 data input different column address than previous 5 address cycles, for 1st plane only different column address than previous 5 address cycles, for 2nd plane only repeat as many times as necessary repeat as many times as necessary draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 59 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance ters to the data registers on the rising edge of we#. r/b# goes low during this transfer time. after the data has been copied into the data registers and r/b# returns high, memory array programming to both planes begins. when r/b# returns high, new data can be written to the cache registers by issuing another two-plane program page cache mode (80h-11h-80h-15h) sequence. the time that r/b# stays low ( t cbsy) is determined by the actual programming time of the previous operation. for the first cache operation, t cbsy duration is the time it takes for the data to be copied from the cache registers to the data registers. on the second and subsequent two-plane program page cache mode operations, transfer from the cache registers to the data registers is delayed until the contents of the current data registers have been programmed into the arrays. if the r/b# pin is used to determine progra mming completion, the last operation of the program sequence must use the two-pl ane program page (80h-11h-80h-10h) command instead of the two-plane prog ram page cache mode (80h-11h-80h- 15h) command. if the two-plane program page cache mode (80h-11h-80h-15h) command is used for the last operation, then use read status (70h or 78h) to monitor the operation's progress; status register bi t 5 indicates when programming is complete. to determine when the current two-plane program page cache mode (80h-11h- 80h-10h) operation has completed, issue the read status (70h) command and check status register bits 5 and 6. when the device is ready, use status register bit 0 to deter- mine if the current operation passed and status register bit 1 to determine if the previous operation passed. if either bit 0 = 1 or bit 1 = 1, indicating a failed operation, then use the two-plane/multiple-die read status (78h) command twice?once for each plane?to determine which current or previous plane operation failed. for more infor- mation on status register bit de finitions, see table 11 on page 33. during the serial data input for either plane, the random data input (85h) com- mand may be used any number of times to change the column address within that plane. draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 60 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance figure 37: two-plane program page cache mode two-plane internal data move 00h-00h-35h/85h-11h-85h-10h a two-plane internal data move operation is similar to an internal data move operation, and requires two sequences. issue a two-plane read for inter- nal data move (00h-00h-35h) command first, then the two-plane program for internal data move (85h-11h-85h-10h) command. data moves are only supported within the planes from which data is read . the first-plane and second-plane addresses must meet the two-plane addressing requirements for both the two-plane read for internal data move (00h-00h-35h) and two-plane program for internal data move (85h-11h-85h-10h) commands (see ?two-plane addressing? on page 53). two-plane read for internal data move 00h-00h-35h the two-plane read for internal data move (00h-00h-35h) command is used in conjunction with the two-plane program for internal data move (85h-11h- 85h-10h) command. first, write 00h to the command register, then write the first-plane internal source address (5 cycles). again, wr ite 00h to the command register, followed by the second-plane internal source address (5 cycles). finally, write 35h to the command register. after the 35h command, r/b# goes low for t r while two pages are read into their respective cache registers. r/b# i/ox 80h address/data input 11h 80h 15h t dbsy t cbsy 1st plane 2nd plane address/data input 1 1 2 r/b# i/ox 80h address/data input 11h 15h t dbsy t cbsy 1st plane 2nd plane address/data input 2 r/b# i/ox 80h address/data input 11h 10h t dbsy t lprog 1st plane 2nd plane address/data input 80h 80h draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 61 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance after a two-plane read for internal data move (00h-00h-35h) command is issued, the data transferred from the source pages into the cache registers may be read out by toggling re#. data is output sequenti ally from the column address originally specified by the two-plane read for in ternal data move (00h-00h-35h) com- mand, starting with plane 0. a two-plane random data read (06h-e0h) command can be used to select the data transferred from the source pages of each plane. this command will change the starting column address on only the plane being selected. the column address on the plane moved from will remain unchanged from its previous location. the memory device is now ready to acce pt the two-plane program for internal data move (85h-11h-85h-10h) command. alternatively, two read for internal data move (00h-35h) commands may be issued, each addressing different planes on the same die, prior to issuing the two- plane program for internal data move (85h-11h-85h-10h) command. two-plane program for internal data move 85h-11h-85h-10h after the two-plane read for internal data move (00h-00h-35h) command has been issued and r/b# goes high (or the st atus register bit 6 is ?1?), the two-plane program for internal data move (85h -11h-85h-10h) command is used. pages must be read from and prog rammed to the same plane. first, write 85h to the command register, th en write the first-plane destination address (5 cycles), then write 11h to the command register. the 11h command is a ?dummy? command that informs the contro l logic that the first set of data for the first plane is complete. no programming of the nand flash array occurs. r/b# goes low for t dbsy, then returns high. the read status (70h) command also indicates that the device is ready when status register bit 6 is set to ?1.? the only valid commands during t dbsy are read status (70h and 78h) and reset (ffh). after t dbsy, write the 85h command to the command register. then write the second- plane destination address (5 cycles), and then write 10h to the command register. data is transferred from the cache registers to the data registers on the rising edge of we#, and programming begins on both planes. r/b# goes low for the duration of array programming time, t prog. when program- ming and verification are complete, r/b# returns high. the read status (70h) com- mand also indicates that the device is ready wh en status register bit 6 is set to ?1.? the only valid commands during t prog are read status (70h and 78h) commands and reset (ffh). if the read status (70h) command indicates an error in the operation (status register bit 0 is ?1?), use the two-plane/mult iple-die read status (78h) command twice?once for each plane?to determine which plane operation failed. during the serial data input for either plane, the random data input (85h) com- mand may be used any number of times to change the column address within that plane. for details on this command, see ?random data input 85h? on page 37. see the example in figure 40 on page 64. draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 62 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance figure 38: two-plane internal data move notes: 1. command can be 70h or 78h. r/b# i/ox 00h 00h address (5 cycles) 35h t r t dbsy 1st-plane source 85h 11h address (5 cycles) 1st-plane destination address (5 cycles) 2nd-plane source 1 r/b# i/ox 85h 10h address (5 cycles) t prog 2nd-plane destination 70h 1 status 1 draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 63 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance figure 39: two-plane internal data move with two-plane random data read notes: 1. command can be 70h or 78h. r/b# re# i/ox r/b# re# i/ox r/b# re# i/ox 00h 00h address (5 cycles) 35h (or 30h) t r 1st-plane source data output data from 1st-plane source address (5 cycles) 2nd-plane source e0h address (2 cycles) 06h e0h address (5 cycles) 2nd-plane source address data from 2nd-plane source 2nd-plane source column address 05h data output 11h t dbsy data output data from 2nd-plane source from new column address 85h 85h 10h address (5 cycles) 2nd-plane destination address (5 cycles) 1st-plane destination 2 2 t prog 70h 1 status 1 1 optional draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 64 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance figure 40: two-plane internal data move with random data input notes: 1. command can be 70h or 78h. two-plane block erase 60h-d1h-60h-d0h the two-plane block erase (60h-d1h-60h-d0h) operation is similar to the block erase (60h-d0h) operation. it erases two blocks instead of one. the blocks to be erased must be on different planes on the same die. the first-plane and second-plane addresses must meet the two-plane addressing requirements (see ?two-plane addressing? on page 53). to begin the two-plane block erase operat ion, write the 60h command to the com- mand register, followed by 3 address cycles of the first-plane block address. next, write the d1h command. the d1h command is a ?dummy? command. r/b# goes low for t dbsy, then returns high. the read status (70h) command also indicates that the device is ready when the status register bit 6 is set to ?1.? the only valid commands dur- ing t dbsy are read status (70h and 78h) and reset (ffh). after t dbsy, write the 60h command to the command register followed by 3 address cycles for the second plane. finally, issue the d0h command. r/b# goes low for the dura tion of block erase time, t bers. when block erasure is com- plete, r/b# returns high. a read status command also indicates that the device is ready when status register bit 6 is set to ?1.? the only valid commands during t bers are read status (70h, 78h) commands and reset (ffh). if the read status (70h) command indicates an error in the operation (status register bit 0 is ?1?), then use the two-plane/mu ltiple-die read status (78h) command twice?once for each plane?to determine which plane operation failed. alternatively, the d1h command may be omitted. in this case, there is no t dbsy time. r/b# i/ox 00h 00h address (5 cycles) 35h t r t dbsy 1st-plane source 1st-plane destination 2nd-plane destination 85h data data address (5 cycles) data optional 85h 11h address (2 cycles) unlimited number of repetitions address (5 cycles) 2nd-plane source 1 r/b# i/ox t prog data data address (5 cycles) 85h 10h 70h 1 status address (2 cycles) 1 data optional unlimited number of repetitions 85h draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 65 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance figure 41: two-plane block erase operation notes: 1. command can be 70h or 78h. re# ce# ale cle i/ox r/b# we# t dbsy status 70h 1 t bers 1st plane 2nd plane optional don?t care address input (3 cycles) d0h 60h d1h address input (3 cycles) 60h draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 66 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance two-plane/multiple-die read status 78h in micron nand flash devices that have two planes and possibly more than one die in a package that share the same ce# pin, it is po ssible to independently poll the status regis- ter of a particular plane and die using the two-plane/multiple-die read status (78h) command. this feature operates regardless of device size, organization, or status. this command can be used to check the stat us during and after two-plane operations and also to check the status of interleaved die operations. after the 78h command is issued, the device requires 3 address cycles containing the block and page addresses, ba[18:6] and pa[5:0]. the most significant block address bit in the third address cycle, ba18, selects the proper die, and the least significant block address bit in the first address cycle, ba6, selects the proper plane within that die. after the 78h command and the 3 address cycl es, the status register is output on i/o[7:0] when re# is low. changes in the status register will be seen on i/o[7:0] as long as ce# and re# are low; it is not necess ary to issue a new two-plane/multiple-die read status command to see these changes. the status register bit definitions are identical to those reported by the read status command (see table 11 on page 33). in devices that have more than one die sharing a common ce# pin, when one die is not busy (status register bit 5 is ?1?), it is possib le to initiate a new operation to that die even if the other die is busy. see ?interleaved die operations? on page 67. use of the two-plane/multiple-die read status (78h) command is prohibited during and following power-on reset and otp commands. figure 42: two-plane/multiple-die read status cycle 78h address (3 cycles) status output t whr t ar t rea ce# cle we# ale re# i/ox draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 67 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance interleaved die operations in devices that have more than one die sharin g a common ce# pin, it is possible to sig- nificantly improve performance by interleavi ng operations between the die. when both die are idle (r/b# is high or status register bit 5 is ?1?), issue a command to the first die. then, while the first die is busy (r/b# is low), issue a command to the other die. there are two methods to determine operatio n completion. the r/b# signal indicates when both die have finished their operatio ns. r/b# remains low while either die is busy. when r/b# goes high, then both die are idle and the operations are complete. alternatively, the two-plane/multiple-die read status (78h) command can report the status of each die individually. if a die is performing a cache operation, like program page cache mode (80h-15h) or two-plane program page cache mode (80h-11h-80h-15h), then the die is able to accept the data for another cache operation when status register bit 6 is ?1.? all operations, including cache operations, are complete on a die when status register bit 5 is ?1.? during and following interleaved die operations, the read status (70h) command is prohibited. instead, use the 78h command to monitor status. these commands select which die will report status. interleaved two-plane commands must also meet the requirements in ?two-plane addressing? on page 53. page read, two-plane page read, program page, program page cache mode, two-plane program page, two-plane program page cache mode, read for internal data move, two-plane read for internal data move, program for internal data move, two-plane program for internal data move, block erase, and two-plane block erase can be used in any combination as interleaved operations on sepa rate die that share a common ce#. in interleaved program and read operat ions, the program operation must be issued before the read operation. the data from the read operation must be read out before the next program operation. interleaved page read operations figure 43 on page 68 shows how to perform interleaved page read operations. in figure 43, the status register is monitore d for operation completion with the two- plane/multiple die read status (78h) command. during interleaved page read operatio ns, a two-plane/multiple-die read sta- tus (78h) command is required before reading data from either die. this ensures that only the die selected by the 78h command re sponds to a subsequent toggle of the re# signal after data output is selected with the 00h command. random data output (05h-e0h) commands are permitted during interleaved page read operations. draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 68 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance figure 43: interleaved page read with status register monitoring address 00h 30h address data out address 00h 30h die 1 die 1 die 1 data out die 2 die 2 address die 2 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) 78h 78h 00h 00h status status draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 69 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance interleaved two-plane page read operation figure 44 on page 70 shows how to perform interleaved two-plane page read opera- tions. in figure 44, the two-plane/mulitple die read status (78h) command is used to monitor the status regi ster for operation completion. the interleaved two-plane page read oper ation must meet tw o-plane addressing requirements. see ?two-plane addressing? on page 53 for details. random data output (05h-e0h) is permit ted during interleaved two-plane page read operations to change the column a ddress within a plane. two-plane random data output (06h-e0h) is permitted du ring interleaved two-plane page read operations to change planes and co lumn addresses between the planes. draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 70 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance figure 44: interleaved two-plane page read with status register monitoring notes: 1. two-plane addressing requirements apply. address 00h 00h address 00h 00h address 30h address 30h die 1 die 2 die 1 die 2 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) address die 1 78h status i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) data output die 1, plane 0 data output die 1, plane 1 address die 1, plane 0 06h e0h address die 1, plane 1 06h e0h address die 2 78h status i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) data output die 2, plane 0 data output die 2, plane 1 data output die 2, plane 1 address die 2, plane 1 06h e0h address 2 cycles 05h e0h address die 2, plane 0 06h e0h 1 2 2 1 draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 71 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance interleaved program page operations figure 45 shows how to perform interleaved program page operations. the status reg- ister is monitored for operation comple tion with the two-plane/multiple-die read status (78h) command. random data input (85h) is permitted during interleaved program page opera- tions. figure 45: interleaved program page with status register monitoring interleaved program page cache mode operations figure 46 shows how to perform interl eaved program page cache mode opera- tions. the status register is monitored with the two-plane/multiple-die read sta- tus (78h) command. random data input (85h) is permitted during interleaved program page cache mode operations. figure 46: interleaved program page cach e mode with status register monitoring data address 80h 10h data address 80h 10h die 1 die 2 status address data address 80h 10h die 1 die 1 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) 78h data address 80h 15h data address 80h 15h die 1 die 2 status address data address 80h 15h die 1 die 1 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) 78h draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 72 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance interleaved two-plane program page operation figure 47 on page 73 shows how to perform interleaved two-plane program page operations. the two-plane/multiple-die re ad status (78h) command is used to monitor the status register for operation completion. the interleaved two-plane program page operation must meet two-plane address- ing requirements. see ?two-plane addressing? on page 53 for details. random data input (85h) is permitted during interleaved two-plane program page operations. draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 73 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance figure 47: interleaved two-plane progra m page with status register monitoring notes: 1. two-plane addressing requirements apply. 1 data address 80h 11h data address 80h 10h die 1 die 1 data address 80h 11h data address 10h die 2 die 2 address data address 80h 11h die 1 die 1 data address 10h address die 1 data address 80h 11h die 2 die 2 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) status status i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) 78h 78h 1 80h 80h draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 74 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance interleaved two-plane program page cache mode operations figure 48 on page 75 shows how to perform interleaved two-plane program page cache mode operations. the status register is monitored with the two-plane/mul- tiple-die read status (78h) command. the interleaved two-plane program page cache mode operation must meet two-plane addressing requirements. see ?two-plane addressing? on page 53 for details. random data input (85h) is permitted during interleaved two-plane program page cache mode operations. draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 75 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance figure 48: interleaved two-plane program page cache mode with status register monitoring notes: 1. two-plane addressing requirements apply. 1 1 data address 80h 11h data address 80h 15h die 1 die 1 data address 80h 11h data address 15h die 2 die 2 address data address 80h 11h die 1 die 1 data address 15h address die 1 data address 80h 11h die 2 die 2 status status 78h 78h 80h 80h i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 76 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance interleaved read for internal data move operations figure 49 on page 77 shows how to perfor m interleaved read for internal data move operations. in figure 49, the status register is monitored for operation comple- tion with the two-plane/multiple-die read status (78h) command. the read for internal data move operatio ns must operate within the same plane. random data output (05h-e0h) commands are permitted during interleaved read for internal data move operations. draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 77 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance figure 49: interleaved read for internal data move with status register monitoring address 00h 35h address data out address 00h 35h die 1 die 1 die 1 data out die 2 die 2 address die 2 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) 78h 78h 00h 00h status status draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 78 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance interleaved two-plane read for internal data move operations figure 50 on page 79 shows how to perform interleaved two-plane read for inter- nal data move operations. in figure 50, the two-plane/multiple-die read sta- tus (78h) command is used to monitor the status register for operation completion. the interleaved two-plane read for internal data move operation must meet two-plane addressing requirements. see ?two-plane addressing? on page 53 for details. the two-plane read for internal data move operations must operate within the same plane. random data output (05h-e0h) is permit ted during interleaved two-plane read for internal data move operations to change the column address within a plane. two-plane random data output (06h-e0h ) is permitted during interleaved two- plane read for internal data move operations to change planes and column addresses between the planes. draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 79 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance figure 50: interleaved two-plane read for internal data move with status register monitoring notes: 1. two-plane addressing requirements apply. address 00h 00h address 00h 00h address 35h address 35h die 1 die 2 die 1 die 2 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) address die 1 78h status i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) data output die 1, plane 0 data output die 1, plane 1 address die 1, plane 0 06h e0h address die 1, plane 1 06h e0h address die 2 78h status i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) data output die 2, plane 0 data output die 2, plane 1 data output die 2, plane 1 address die 2, plane 1 06h e0h address 2 cycles 05h e0h address die 2, plane 0 06h e0h 1 2 2 1 draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 80 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance interleaved program for inte rnal data move operations figure 51 shows how to perform interlea ved program for internal data move operations. in figure 51, the status register is monitored for operation completion with the two-plane/multiple-die read status (78h) command. an interleaved read for internal data move operation is required before a pro- gram for internal data move operation ca n be started. see ?interleaved read for internal data move operations? on page 76 for a description. the program for internal data move operations must operate within the same plane. random data input (85h) commands are permitted during interleaved program for internal data move operations. figure 51: interleaved progra m for internal data move with status register monitoring notes: 1. a previous interleaved read for internal data move operation is required. interleaved two-plane program for internal data move operations figure 52 on page 81 shows how to perf orm interleaved two-plane program for internal data move operations. in figure 52, the two-plane/multiple-die read status (78h) command is used to moni tor the status register for operation com- pletion. the interleaved two-plane program for internal data move operation must meet two-plane addressing requirements. see ?two-plane addressing? on page 53 for details. the two-plane program for intern al data move operations must oper- ate within the same plane. an interleaved two-plane read for internal data move operation is required before a two-plane program for internal data move operation can be started. see ?interleaved two-plane read for internal data move operations? on page 78 for a description. random data input (85h) is permitted during interleaved two-plane program for internal data move operations. data address 85h 10h data address 85h 10h die 1 die 2 status address die 1 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) 78h status address 78h die 2 draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 81 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance figure 52: interleaved two-plane program for inte rnal data move with status register monitoring notes: 1. a previous interleaved two-plane read fo r internal data move operation is required. 1 data address 85h 11h data address 85h 10h die 1 die 1 data address 85h 11h data address 10h die 2 die 2 address data address 85h 11h die 1 die 1 data address 10h address die 1 data address 85h 11h die 2 die 2 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) status status i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) 78h 78h 1 85h 85h note 1 note 1 draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 82 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance interleaved block erase operations figure 53 shows how to perform interl eaved block erase operations. the two- plane/multiple-die read status (78h) co mmand is used to monitor the status register for operation completion. figure 53: interleaved block erase with status register monitoring address 60h d0h die 1 address 60h d0h die 2 address status die 1 address 60h d0h die 1 i/ox r/b# (die 1 internal) r/b# (die 2 internal) r/b# (external) 78h draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 83 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance interleaved two-plane block erase operations figure 54 shows how to perform interlea ved two-plane block erase operations. the two-plane/multiple-die read status (78h) command is used to monitor the status register for operation completion. the interleaved two-plane block erase oper ation must meet two-plane addressing requirements. see ?two-plane addressing? on page 53 for details. figure 54: interleaved two-plane block erase with status register monitoring notes: 1. two-plane addressing requirements apply. address 60h die 1 (optional) die 2 (optional) d1h address 60h die 1 d0h address address die 2 d0h 60h d1h address 78h die 1 address die 1 60h address die 1 60h d1h d0h address die 2 78h status status i/ox r/b# (die 1 internal) r/b# (die 2 internal r/b# (external) i/ox r/b# (external) 1 1 60h r/b# (die 1 internal) r/b# (die 2 internal) draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 84 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance reset operation reset ffh the reset (ffh) command is used to put th e memory device into a known condition and to abort a command sequence in progress. read, program, and erase commands can be aborted while the device is in the busy state. the contents of the memory location being programmed or the block being erased are no longer valid. the data may be partiall y erased or programmed, and is invalid. the command register is cleared and is ready for the next command. the data register and cache register contents are invalid. the status register contains the value e0h when wp# is high; otherwise it is written with a 60h value. r/b# goes low for trst after the reset command is written to the command register (see figure 55 and table 16 on page 85). the reset command must be issued to all ce#s as the first command after power-on. the device will be busy for a maximum of 1ms. during and following the initial reset command, and prior to issuing the next command, use of the two plane/multiple- die read status (78h) command is prohibited. if the reset command is issued during or following an interleaved-die operation then the two-plane/multiple-die read status (78h) command must be issued, once per die, to determine completion of the re set operation. use of the read status (70h) command is not permitted until the 78h command is issued. draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 85 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance figure 55: reset operation table 16: status register contents after reset operation condition status bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 hex wp# high ready 11100000e0h wp# low ready and write protected 0110000060h cle ce# w e# r/b# i/ox t rst t wb ffh reset command draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 86 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance write protect operation it is possible to enable and disable program and erase commands using wp#. figures 56 through 67 illu strate the setup time ( t ww) required from wp# toggling until a program or erase command is latched in to the command register. after command cycle 1 is latched, wp# must not be toggled until the command is complete and the device is ready (status register bit 5 is ?1?). figure 56: erase enable figure 57: erase disable figure 58: program enable figure 59: program disable t ww 60h d0h we# i/ox wp# r/b# t ww 60h d0h we# i/ox wp# r/b# t ww 80h 10h or 15h we# i/ox wp# r/b# t ww 80h 10h or 15h we# i/ox wp# r/b# draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 87 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance figure 60: program for internal data move enable figure 61: program for internal data move disable figure 62: two-plane erase enable figure 63: two-plane erase disable t ww 85h 10h we# i/ox wp# r/b# t ww 85h 10h we# i/ox wp# r/b# t ww 60h 60h d1h d0h we# i/ox wp# r/b# t ww 60h 60h d1h d0h we# i/ox wp# r/b# draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 88 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory command definitions micron confidential and proprietary advance figure 64: two-plane program enable figure 65: two-plane program disable figure 66: two-plane program for internal data move enable figure 67: two-plane program for internal data move disable t ww 80h 11h 80h 10h or 15h we# i/ox wp# r/b# t ww 80h 11h 80h 10h or 15h we# i/ox wp# r/b# t ww 85h 11h 85h 10h we# i/ox wp# r/b# t ww 85h 11h 85h 10h we# i/ox wp# r/b# draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 89 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory error management micron confidential and proprietary advance error management this nand flash device is specified to have the minimum number of valid blocks (n vb ) of the total available blocks per die shown in table 21 on page 92. this means the devices may have blocks that are invalid when shipped from the factory. an invalid block is one that contains at least one page that ha s more bad bits than can be corrected by the minimum required ecc. additional bad blocks may develop with use. however, the total number of available blocks will not fall below n vb during the endurance life of the prod- uct. although nand flash memory devices may contain bad blocks, they can be used reli- ably in systems that provide bad-block management and error-correction algorithms. this ensures data integrity. internal circuitry isolates ea ch block from other blocks, so the presence of a bad block does not affect the operation of the rest of the nand flash array. nand flash devices are shipped from the factory erased. the factory identifies invalid blocks before shipping by attempting to pr ogram the bad-block mark into every location in the first page of each invalid block. it may not be possible to program every location in an invalid block with the bad-block mark. however, the first spare area location in each bad block is guaranteed to contain the bad- block mark. this method is compliant with onfi factory defect mapping requirements. see table 17 for the bad-block mark. system software should initially check the firs t spare area location on the first page of each block prior to performing any progra m or erase operations on the nand flash device. a bad- block table can then be created, enabling system software to map around these areas. factory testing is performed under worst-case conditions. because invalid blocks may be marginal, it may not be possible to recover the bad-block marking if the block is erased. over time, some memory locations may fail to program or erase properly. in order to ensure that data is stored properly over the life of the nand flash device, the following precautions are required: ? check status after each program and erase operation. ? under typical conditions, use the minimum required ecc shown in table 17. ? use bad-block management an d wear-leveling algorithms. the first block (physical block address 00h) for each ce# is guaranteed to be valid with ecc when shipped from the factory. table 17: error management details description requirement minimum number of valid blocks (n vb )4,016 total available blocks per die 4,096 minimum required ecc 1-bit ecc per 539 bytes of data first spare area location x8: byte 4,096 bad-block mark x8: 00h draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 90 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory electrical characteristics micron confidential and proprietary advance electrical characteristics stresses greater than those listed under ?absolute maximum ratings? may cause perma- nent damage to the device. this is a stress rating only, and functional operation of the device at these or any other conditions abov e those indicated in the operational sections of this specification is not guaranteed. exposure to absolute maximum rating conditions for extended periods ma y affect reliability. v cc power cycling micron nand flash devices are designed to prevent data corruption during power tran- sitions. v cc is internally monitored. (the wp# signal permits additional hardware pro- tection during power transitions.) when v cc reaches 2.5v for a 3v device, a minimum of 100s should be allowed for the flash device to initialize before any commands are exe- cuted (see figure 68 on page 91 for the states of signals during v cc power cycling). both of the following conditions must be satisfied before r/b# will be valid: ? 50s have elapsed since vcc started its ramp. ? 10s have elapsed since vcc reached 2.5v the reset command must be issued to all ce#s as the first command after the nand flash device is powered on. each ce# will be busy for a maximum of 1ms after a reset command is issued. each nand die will draw no more than i st prior to execution of the first reset com- mand after the device is powered on. each nand die will draw no more than 10ma of current during the execution of the first reset command after the device is powered on. table 18: absolute maximum ratings by device voltage on any pin relative to v ss parameter/condition symbol min max unit voltage input v in ?0.6 +4.6 v v cc supply voltage v cc ?0.6 +4.6 v storage temperature t stg ?65 +150 c short circuit output current, i/os ?5ma table 19: recommended operating conditions parameter/condition symbol min typ max unit operating temperature commercial t a 0 ? +70 c extended ?40 ? +85 c v cc supply voltage v cc 2.7 3.3 3.6 v ground supply voltage v ss 000v draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 91 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory electrical characteristics micron confidential and proprietary advance figure 68: ac waveforms during power transitions 100s (min) un d efine d don?t c are ffh 1ms (max) 10s (max) 50s (max) 3v d evi c e: 2.5v 3v d evi c e: 2.5v t cs v cc c le c e# wp# we# ale re# i/ox r/b# draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 92 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory electrical characteristics micron confidential and proprietary advance notes: 1. test conditions for v oh and v ol . 2. dc characteristics may need to be relaxed if r/b# pull-down strength is not set to ?full.? see table 15 on page 51 fo r additional details. 3. measurement is taken with 1ms aver aging intervals and begins after v cc reaches v cc (min). 4. this is for single-die operations. it ca n be greater for interleaved die operations. notes: 1. invalid blocks are blocks that contain on e or more bad bits beyond ecc. the device may contain bad blocks upon shipment. additional bad blocks may develop over time; how- ever, the total number of availabl e blocks will not drop below n vb during the endurance life of the device. do not erase or prog ram blocks marked invalid by the factory. 2. block 00h (the first block per each chip enable ) is guaranteed to be valid with ecc when shipped from the factory. 3. each 8gb section has a maximum of 80 invalid blocks. 4. each 16gb section has a maximum of 160 invalid blocks, not to exceed 80 invalid blocks for each nand flash die. table 20: device dc and operating characteristics parameter conditions symbol min typ max unit notes sequential read current t rc = t rc (min); ce# = v il ; i out = 0ma i cc 1? 20 30ma4 program current ?i cc 2? 20 30ma4 erase current ?i cc 3? 20 30ma4 current during first reset command after power-on ?i cc 4? ? 10ma4 standby current (ttl) ce# = v ih ; wp# = 0v/v cc i sb 1? ? 1 ma standby current (cmos) ce# = v cc ? 0.2v; wp# = 0v/v cc i sb 2? 10 50a input leakage current v in = 0v to v cc i li ? ? 10 a output leakage current v out = 0v to v cc i lo ? ? 10 a staggered power-up current rise time = 1ms line capacitance = 0.1f i st ? ? 10 per die ma 3 input high voltage i/ox, ce#, cle, ale, we#, re#, wp# v ih 0.8 x v cc ?v cc + 0.3 v input low voltage (all inputs) ?v il ?0.3 ? 0.2 x v cc v output high voltage i oh = ?400a v oh 0.67 x v cc ??v1 output low voltage i ol = 2.1ma v ol ??0.4v1 output low current (r/b#) v ol = 0.4v i ol (r/b#) 8 10 ? ma 2 table 21: valid blocks parameter symbol device min max unit notes valid block number n vb mt29f8g 4,016 4,096 blocks 1, 2 mt29f16g 8,032 8,192 blocks 1, 2, 3 mt29f32g 16,064 16,384 blocks 1, 2, 4 mt29f64g 32,128 32,768 blocks 1, 2, 4 draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 93 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory electrical characteristics micron confidential and proprietary advance notes: 1. these parameters are verified in device characterization and are not 100 percent tested. 2. test conditions: t c = 25c; f = 1 mhz; v in = 0v. notes: 1. verified in device charac terization; not 100 percent tested. notes: 1. operating-mode timings meet onfi timing mode 5 parameters. 2. timing for t adl begins in the address cy cle, on the final rising edge of we#, and ends with the first rising edge of we# for data input. table 22: capacitance description symbol device max unit notes input capacitance c in mt29f8g 5 pf 1, 2 mt29f16g 10 mt29f32g 20 mt29f64g 20 input/output capacitance (i/o) c out mt29f8g 5 pf 1, 2 mt29f16g 10 mt29f32g 20 mt29f64g 20 table 23: test conditions parameter value notes input pulse levels mt29fxxg08xaa 0.0v to 3.3v input rise and fall times 5ns input and output timing levels v cc /2 output load mt29fxxg08xaa (v cc = 3.0v 10%) 1 ttl gate and cl = 50pf 1 mt29fxxg08xaa (v cc = 3.3v 10%) 1 ttl gate and cl = 100pf 1 table 24: ac characteristics: command, data, and address input parameter symbol min 1 max 1 unit notes ale to data start t adl 70 ? ns 2 ale hold time t alh 5?ns ale setup time t als 10 ? ns ce# hold time t ch 5?ns cle hold time t clh 5?ns cle setup time t cls 10 ? ns ce# setup time t cs 15 ? ns data hold time t dh 5?ns data setup time t ds 7?ns write cycle time t wc 20 ? ns we# pulse width high t wh 7?ns we# pulse width t wp 10 ? ns wp# setup time t ww 30 ? ns draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 94 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory electrical characteristics micron confidential and proprietary advance notes: 1. operating-mode timings meet onfi timing mode 5 parameters. 2. transition is measured 200mv from steady-sta te voltage with load. this parameter is sam- pled and not 100 percent tested. 3. ac characteristics may need to be relaxed if i/o drive strength is not set to ?full.? see table 14 on page 50 for additional details. 4. if reset (ffh) command is loaded at ready state, the device goes busy for maximum 5s. 5. do not issue a ne w command during t wb, even if r/b# is ready. table 25: ac characteristics: normal operation parameter symbol min 1 max 1 unit notes ale to re# delay t ar 10 ? ns change column setup time t ccs 70 ? ns ce# access time t cea ?25ns ce# high to output high-z t chz ?30ns2 cle to re# delay t clr 10 ? ns ce# high to output hold t coh 15 ns cache busy in page read cache mode (first 31h) t dcbsyr1 ?5s cache busy in page read cache mode (next 31h and 3fh) t dcbsyr2 t dcbsyr1 25 s output high-z to re# low t ir 0?ns data transfer from flash array to data register t r ?25s read cycle time t rc 20 ? ns re# access time t rea ?16ns3 re# high hold time t reh 7?ns3 re# high to output hold t rhoh 15 ? ns 3 re# high to we# low t rhw 100 ? re# high to output high-z t rhz ? 100 ns 2, 3 re# low to output hold t rloh 5ns re# pulse width t rp 10 ? ns ready to re# low t rr 20 ? ns reset time (read/program/erase) t rst ? 5/10/500 s 4 we# high to busy t wb ?100ns 5 we# high to re# low t whr 60 ? ns draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 95 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory electrical characteristics micron confidential and proprietary advance notes: 1. four total to the same page. 2. t cbsy max time depends on timi ng between internal progra m completion and data in. 3. t lprog = t prog (last page) + t prog (last - 1 page) - comman d load time (last page) - address load time (last page) - data load time (last page). table 26: program/erase characteristics symbol parameter typ max unit notes nop number of partial-page programs ? 4 cycles 1 t bers block erase operation time 1.5 3 ms t cbsy busy time for cache program operation 20 700 s 2 t dbsy dummy busy time for two-plane operations 0.5 1 s t feat busy time for set features and get features operations ?1s t lprog last page program operation time ???3 t obsy busy time for otp data program operation if otp is protected ?25s t prog program page operation time 250 700 s draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 96 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory timing diagrams micron confidential and proprietary advance timing diagrams figure 69: command latch cycle figure 70: address latch cycle we# ce# ale cle i/ox command t wp t ch t cs t alh t dh t ds t als t clh t cls don?t care we# ce# ale cle i/ox col add 1 t wp t wh t cs t dh t ds t als t alh t cls col add 2 row add 1 row add 2 row add 3 don?t care undefined t wc draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 97 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory timing diagrams micron confidential and proprietary advance figure 71: input data latch cycle notes: 1. d in final = 4,313 (x8) w e# ce# ale cle i/ox t wp t wp t wp t wh t als t dh t ds t dh t ds t dh t ds t clh t ch d in 1 d in final 1 don?t care t wc d in 0 draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 98 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory timing diagrams micron confidential and proprietary advance figure 72: serial access cycle after read note: use this timing diagram for t rc 30ns. figure 73: serial access cycle after read (edo mode) note: use this timing diagram for t rc < 30ns. ce# re# i/ox t reh t rp t rr t rc t cea t rea t rea t rea don?t care t rhz t chz t rhz t rhoh r/b# t coh d out d out d out d out d out d out ce# re# i/ox r/b# t rr t cea t rea t rp t reh t rc t rloh t rea t rhoh t rhz t coh t chz don?t care draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 99 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory timing diagrams micron confidential and proprietary advance figure 74: read status cycle figure 75: two-plane/multiple-die read status operation re# ce# w e# cle i/ox t rhz t wp t whr t clr t ch t cls t cs t clh t dh t rp t chz t ds t rea t rhoh t ir 70h status output don?t care t cea t coh t whr t ar ce# cle w e# ale re# i/ox don?t care 78h row add 1 row add 2 row add 3 status output t ds t dh t wp t wp t wc t ch t als t alh t wh t cls t clh t alh t cs t cea t chz t rea t rhoh t rhz t coh draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 100 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory timing diagrams micron confidential and proprietary advance figure 76: page read operation figure 77: read operation with ce# ?don?t care? d out n d out n + 1 d out m we# ce# ale cle re# r/b# i/ox t wc busy 00h 30h t r t wb t ar t rr t rp t clr t rc t rhz don?t care col add 1 col add 2 row add 1 row add 2 row add 3 re# ce# t rea t chz t coh t cea re# ce# ale cle i/ox i/ox out r/b# we# data output t r don?t care address (5 cycles) 00h 30h draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 101 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory timing diagrams micron confidential and proprietary advance figure 78: random data read operation we# ce# ale cle re# r/b# i/ox busy col add 1 col add 2 row add 1 row add 2 row add 3 00h t wb t rhw t ar t rr don?t care t rc d out m d out m + 1 col add 1 col add 2 05h e0h t rea t clr d out n d out n + 1 30h t ccs column address n column address m t r draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 102 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory timing diagrams micron confidential and proprietary advance figure 79: page read cache mode operation, part 1 of 2 t wc we# ce# ale cle re# r/b# i/ox column address 0 1 d out page address m page address m column address 00h t cea t ds t clh t cls t cs t ch t dh don?t care t rr t wb t r t dcbsyr2 column address 0 continued to 1 of next page t rc t rea 30h d out 0 31h 31h col add 2 row add 1 row add 2 row add 3 00h t dcbsyr1 page address m + 1 col add 1 t rhw d out 1 d out 0 draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 103 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory timing diagrams micron confidential and proprietary advance figure 80: page read cache mode operation, part 2 of 2 we# ce# ale cle re# r/b# i/ox 1 page address m + 1 don?t care page address m + 2 column address 0 page address m + x column address 0 t clh t ch t rea t cea t rhw t rhw t ds t dh t rr t dcbsyr2 t dcbsyr2 t wb column address 0 d out 0 d out 1 d out 31h d out 0 d out 1 d out d out 0 d out 1 d out 3fh t cls t cs t rc d out 31h t dcbsyr2 continued from 1 of next page draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 104 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory timing diagrams micron confidential and proprietary advance figure 81: page read cache mode operation without r/b#, part 1 of 2 t wc we# ce# ale cle re# i/ox 30h 70h status d out 0 column address 0 1 d out 0 d out 1 d out column address 00h page address m page address m t cea t ds t clh t cls t cs t ch t dh don?t care 31h 31h column address 0 70h status i/o 6 = 0, cache busy = 1, cache ready i/o 5 = 0, busy = 1, ready continued to 1 of next page col add 1 col add 2 row add 1 row add 2 row add 3 00h 00h 00h t rc t rea 70h status i/o 6 = 0, cache busy = 1, cache ready page address m + 1 t rhw t rhw t rhw draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 105 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory timing diagrams micron confidential and proprietary advance figure 82: page read cache mode operation without r/b#, part 2 of 2 we# ce# ale cle re# i/ox 1 page address m + 1 don?t care page address m + 2 column address 0 continued from 1 of previous page page address m + x column address 0 t rea t ds t dh column address 0 d out 0 d out 1 d out 31h d out 0 d out 3fh d out 1 d out d out 1 d out 0 t rc d out 31h 70h status i/o 6 = 0, cache busy = 1, cache ready 70h status i/o 6 = 0, cache busy = 1, cache ready 70h status i/o 6 = 0, cache busy = 1, cache ready 00h 00h 00h t clh t cls t cs t rhw t rhw t rhw t rhw draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 106 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory timing diagrams micron confidential and proprietary advance figure 83: read id operation note: see table 9 on page 27 for actual values. figure 84: program page operation we# ce# ale cle re# i/ox address, 1 cycle 90h 00h or 20h byte 2 byte 0 byte 1 byte 3 byte 4 t ar t rea t whr we# ce# ale cle re# r/b# i/ox t wc t adl serial data input command x8 device: m = 4,314 bytes program command read status command 1 up to m byte serial input 80h col add 1 col add 2 row add 1 row add 2 row add 3 d in n d in m 70h status 10h t prog t whr t wb don?t care draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 107 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory timing diagrams micron confidential and proprietary advance figure 85: program operation with ce# ?don?t care? figure 86: program page operation with random data input cle ce# we# ale i/ox address (5 cycles) data input 10h we# ce# t wp t ch t cs don?t care data input 80h we# ce# ale cle re# r/b# i/ox t wc serial data input command serial input 80h col add 1 col add 2 row add 1 row add 2 row add 3 d in n d in n+1 t adl t ccs random data input command column address program command read status command serial input 85h t prog t wb t whr don?t care col add 1 col add 2 d in n d in n+1 70h status 10h draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 108 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory timing diagrams micron confidential and proprietary advance figure 87: internal data move operation figure 88: program page cache mode operation we# ce# ale cle re# r/b# i/ox t wb t prog t wb busy busy read status command t wc internal data move don?t care t adl t whr col add 2 row add 1 row add 2 70h 10h status data n row add 3 col add 1 00h 35h col add 2 row add 1 row add 2 row add 3 col add 1 85h data 1 t r we# ce# ale cle re# r/b# i/ox 15h t cbsy t wb t wb t whr t lprog col add 1 80h 10h 70h status col add 2 row add 2 row add 1 col add 1 col add 2 row add 2 row add 1 row add 3 d in m d in n d in m d in n last page - 1 last page serial data input serial input program program t wc don?t care 80h t adl row add 3 draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 109 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory timing diagrams micron confidential and proprietary advance figure 89: program page cache mode operation ending on 15h we# ce# ale cle re# i/ox 15h col add 1 80h 15h 70h status 70h status 70h status col add 2 row add 2 row add 1 row add 3 col add 1 col add 2 row add 2 row add 1 row add 3 d in m d in n d in m d in n last page last page ? 1 serial data input serial input program program t wc don?t care 80h poll status until: i/o6 = 1, ready to verify successful completion of the last 2 pages: i/o5 = 1, ready i/o0 = 0, last page program successful i/o1 = 0, last page ? 1 program successful t adl t whr t whr t adl draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 110 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory timing diagrams micron confidential and proprietary advance figure 90: block erase operation figure 91: reset operation we# ce# ale cle re# r/b# i/ox auto block erase setup command erase command read status command busy row address 60h row add 1 row add 2 row add 3 70h status d0h t wc t bers t wb t whr don?t care i/o0 = 0, pass i/o0 = 1, fail cle ce# w e# r/b# i/ox t rst t wb ffh reset command draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 111 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory tsop package information micron confidential and proprietary advance tsop package information figure 92: 48-pin tsop type 1 (wp package code) package diagram note: all dimensions are in millimeters. 1.20 max 0.15 +0.03 -0.02 0.27 max 0.17 min see detail a 18.40 0.08 20.00 0.25 detail a 0.50 0.1 0.80 0.10 +0.10 -0.05 0.10 0.25 gage plane 0.25 for reference only 0.50 typ for reference only 12.00 0.08 1 24 48 25 plated lead finish: 100% sn mold compound: epoxy novolac package width and length do not include mold protrusion. allowable protrusion is 0.25 per side. draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 112 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory vlga package information micron confidential and proprietary advance vlga package information figure 93: 52-pad vlga notes: 1. all dimensions are in millimeters. 2. solder pads are plated with 5-16 microns of nickel followed by a minimum of 1.0 microns of soft wire bondable gold (99.9% pure). 3. primary datum a (seating plane) is defined by the bottom terminal surf ace. metallized test terminal lands or interconnect terminals need not extend below th e package bottom sur- face. pad a1 id seating plane 0.10 a a 1.00 max pad a6 3.00 4.00 2.00 2.00 typ 6.00 12.00 0.10 10.00 5.00 2.00 typ 6.00 0.05 40x ?0.70 0.05 pads ? 0.70 non solder mask defined. 1 12x ?1.00 0.05 pads ? 1.00 non solder mask defined. 1 mold compound: epoxy novolac substrate material: plastic laminate 13.00 12.00 10.00 5.00 6.00 2.00 typ 8.50 0.05 6.50 7.80 17.00 0.10 c l c l ?0.70 pad a1 id pad a1 draft 5/19/2008 ? 8000 s. federal way, p.o. box 6, boise, id 83707-0006, tel: 208-368-3900 prodmktg@micron.com www.micron.com customer comment line: 800-932-4992 micron, the m logo, and the micron logo are trad emarks of micron technology, inc. all other trademarks are the prope rty of their respective owners. advance: this data sheet contains initial de scriptions of products still under development. 8, 16, 32, 64gb nand flash memory llga package information pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__2.fm -rev. 1.9 5/08 en 113 ?2007 micron technology, inc. all rights reserved. micron confidential and proprietary advance llga package information figure 94: 52-pad llga notes: 1. all dimensions are in millimeters. 2. solder pads are plated with 5-16 microns of nickel followed by a minimum of 1.0 microns of soft wire bondable gold (99.9% pure). 3. primary datum a (seating plane) is defined by the bottom terminal surf ace. metallized test terminal lands or interconnect terminals need not extend below th e package bottom sur- face. terminal a1 id seating plane see detail a detail a not to scale 2 0.08 a a 1.47 max 3 4 2 2 typ 6 10 2 typ 40x ?0.7 1 12x ?1 1 mold compound: epoxy novolac substrate material: plastic laminate 13 12 10 5 6 2 typ 6.5 7.8 terminal a1 id see note 3 8 7 6 5 4 3 2 1 0 oa ob oc od oe of a b c d e f g h j k l m n 14 0.15 9 0.08 18 0.15 5 7 0.08 draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__3.fm -rev. 1.9 5/08 en 114 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory revision history micron confidential and proprietary advance revision history rev. 1.11, advance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/19/08 ? table 10, parameter page data structure, on page 28: updated values for bytes 254? 255. ? table 20, device dc and operating characteristics, on page 92: updated i cc 4 param- eter description. rev. 1.10, advance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4/24/08 ? page 1: added part numbers. ? ?features? on page 1: added ?64gb: 32,768 blocks? under organization, device size; updated density, configuration, and package under options. ? figure 2: part number chart on page 2: updated figure. ? ?general description? on page 8: updated description. ? figure 4: pad assignment (top view) 52-pad vlga on page 10: added figure with note. ? figure 5: pad assignment (top view) 52-pad llga on page 11: added figure with note 1 and note 2; updated note 1. ? table 1: signal descriptions on page 12: updated table. ? figure 7: memory map (x8) on page 14: updated figure. ? figure 9: array organization for 32gb and 64 gb x8 on page 16: updated figure title; updated note 2; added note 3. ? table 4: array addressing: 32gb and 64gb x8 on page 16: updated table title. ? ?bus operation? on page 17: updated description. ? ?control signals? on page 17: updated description. ? ?ready/busy#? on page 18: updated description. ? table 8: device id and configuration codes for address 00h on page 26: updated table. ? table 10: parameter page data structure on page 28: updated table. ? ?block erase 60h-d0h? on page 42: updated description. ? ?otp data program a0h-10h? on page 43: changed ? t dbsy? to ? t obsy.? ? ?two-plane addressing? on page 53: changed ?ba7? to ?ba6?; changed ?32gb? to ?64gb.? ? ?error management? on page 89: updated description. ? table 17: error management details on page 89: updated table. ? ?vcc power cycling? on page 90: updated description. ? table 20: device dc and operating characteristics on page 92: updated table. ? table 21: valid blocks on page 92: updated table. ? table 22: capacitance on page 93: updated table. ? table 26: program/erase characteristics on page 95: updated table. ? figure 93: 52-pad vlga on page 112: added figure; added 3 notes under figure. ? figure 94: 52-pad llga on page 113: added figure; added 3 notes under figure. rev. 1.9, advance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10/16/07 ? table 8, device id and configuration codes for address 00h, on page 26: updated table values. draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__3.fm -rev. 1.9 5/08 en 115 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory revision history micron confidential and proprietary advance ? table 10, parameter page data structure, on page 28: removed es and qs part num- bers from columns 44-63 and columns 254-255. ? figure 62: two-plane erase enable on page 87: updated figure. ? figure 63: two-plane erase disable on page 87: updated figure. ? figure 66: two-plane program for internal data move enable on page 88: updated figure. ? figure 67: two-plane program for intern al data move disable on page 88: updated figure. ? ?error management? on page 89: replaced entire section. ? ?vcc power cycling? on page 90: replaced all text. ? table 20, device dc and oper ating characteristics, on pa ge 92: added line describing power-on current requirement. rev. 1.8, advance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8/03/07 ? ?features? on page 1: added ?(contact factory)? to read unique id. ? table 8, device id and configuration codes for address 00h, on page 26: in byte 3, changed serial access (min) to 20ns, and mt29fxxg08 i/o4 to 0. in byte 4, changed plane size to 4gb; changed mt29f8g 08, mt29f16g08, and mt29f32g08 i/o4 to 0. ? ?program page 80h-10h? on page 37, ?program for internal data move 85h- 10h? on page 40, ?two-plane program page 80h-11h-80h-10h? on page 57, ?two-plane program page cache mode 80h-11h-80h-15h? on page 58, ?reset ffh? on page 84: deleted paragraph re effect of issuing reset (ffh) com- mand during operation while r/b# is low. ? ?two-plane/multiple-die read status 78h? on page 66: removed two- plane page read from first paragraph. ? ?reset ffh? on page 84, ?vcc power cycling? on page 90: clarified that reset must be issued to all ce#s as first command after power-on. ? table 24, ac characteristics: command, data, and address input, on page 93: removed program page cache mode operation and notes 1 and 2. ? table 25, ac characteristics: normal operation, on page 94: removed program page cache mode operation and notes 1 and 2. rev. 1.7, advance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7/19/07 ? table 10, parameter page data structure, on page 28: updated table values. ? figure 51: interleaved program for intern al data move with status register monitoring on page 80: revised figure. ? figure 52: interleaved two-plane program for internal data move with sta- tus register monitoring on page 81: revised figure. ? table 22, capacitance, on page 93: inserted device part numbers. rev. 1.6, advance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7/12/07 ? figure 3: pin assignment (top view) 48-pin tsop type 1 on page 9: changed pin 20 from v cc to nc. rev. 1.5, advance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6/29/07 ? figure 8 on page 15, and figure 9 on page 16: plane, device, and die mb values as appropriate. ? table 24, ac characteristics: command, data, and address input, on page 93: updated t wc to 20ns, t wp to 7ns, and t wp to 10ns. rev. 1.4, advance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6/27/07 draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__3.fm -rev. 1.9 5/08 en 116 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory revision history micron confidential and proprietary advance ? figure 2: part number chart on page 2: changed lower end of operating voltage range from 2.5v to 2.7v. ? ?general description? on page 8: changed t prog and t bers references from num- bers to parameters; added paragraph re onfi. ? table 6, command set, on page 22: changed read parameter page to 1 address cycle. ? table 10, parameter page data structure, on page 28: revised bit references and table columns and values. ? ?program page cache mode 80h-15h? on page 38: added sentence re crossing block boundaries. ? ?interleaved page read operations? on page 67: expanded 78h command discus- sion. ? ?vcc power cycling? on page 90: added paragraph re 50s for v cc . ? figure 68: ac waveforms during power transitions on page 91: added 50s (max) to figure. ? table 20, device dc and operating ch aracteristics, on page 92: added i st and notes 3 and 4; added note 4 to i cc 1, i cc 2, and i cc 3. ? table 21, valid blocks, on page 92: revised note 4. ? table 25, ac characteristics: norm al operation, on page 94: changed t r (max) to 50s; removed note 5 for t rloh. ? table 26, program/erase characteristics, on page 95: changed t bers (typ) from 3ms to 2ms; revised t dbsy description. rev. 1.3, advance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/30/07 ? ?features? on page 1: deleted ?(x8 only)? from sequential read and ?(contact fac- tory)? from read unique id, and updated write performance for block erase to 3ms. ? figure 3: pin assignment (top view) 48-pin tsop type 1 on page 9: changed pin 22 from ?nc? to ?dnu?; added ?1.0? to ?onfi? in note 2. ? table 14, feature address 80h: programmable i/o drive strength, on page 50: added three-quarters drive strength option; revised values for one-half and one-quarter drive strength. ? table 16, status register contents after reset operation, on page 85: added three- quarters drive strength option; revised va lues for one-half and one-quarter drive strength; in note, changed ?three? to ?four? in third sentence. ? table 25, ac characteristics: norm al operation, on page 94: changed t ccs (min) from 100ns to 70ns. ? figure 43: interleaved page read with status register monitoring on page 68 and figure 49: interleaved read for internal data move with status register moni- toring on page 77: added 00h after status on i/ox line. ? ?interleaved program page cache mode operations? on page 71: deleted para- graph about random data input. ? table 26, program/erase characteristics, on page 95: changed t bers (typ) from 2ms to 3ms. ? figure 31: get features operatio n on page 51: deleted vertical. ? figure 68: ac waveforms during power transitions on page 91: added ?don?t care? after ?undefined? on r/b#, with 10 s (max) from rising edge of v cc . rev. 1.2, advance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/23/07 ? figure 3: pin assignment (top view) 48-pin tsop type 1 on page 9: added note 2 to pins 25, 34, 39, and 48. draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__3.fm -rev. 1.9 5/08 en 117 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory revision history micron confidential and proprietary advance ? table 10, parameter page data structure, on page 28: revised command names in bytes 8-9 description for bits 4, 3, and 0. ? ?page read cache mode operations? on page 34: changed ? t rcbsyr1? and ? t rcbsyr2? to ? t dcbsyr1? and ? t dcbsyr2.? ? figure 27: otp program with random data input on page 45: in note, changed ?02h?08h? to ?02h?0bh.? ? ?set features efh? on page 52: revised second paragraph. ? figure 32: set features operation on page 52: changed ?ech? to ?efh? and added t adl. ? ?two-plane page read 00h-00h-30h? on page 53: revised description. ? ?interleaved page read operations? and figure 43: interleaved page read with status register monitoring on page 68: added description and diagram. ? ?interleaved two-plane page read operation? on page 69 and figure 44: inter- leaved two-plane page read with status register monitoring on page 70: added description and diagram. ? ?interleaved read for internal data move operations? and figure 49: inter- leaved read for internal data move with status register monitoring on page 77: added description and diagram. ? ?interleaved two-plane read for internal data move operations? on page 78 and figure 50: interleaved two-plane read for internal data move with status register monitoring on page 79: added description and diagram. ? ?interleaved program for internal data move operations? and figure 51: inter- leaved program for internal data move with status register monitoring on page 80: added description and diagram. ? ?interleaved two-plane program for internal data move operations? on page 80 and figure 52: interleaved two-plane program for internal data move with status register monitoring on page 81: added description and diagram. ? table 20, device dc and operating characte ristics, on page 92: added notes 1 and 2. ? table 21, valid blocks, on page 92: revi sed note 2 re first-block guarantee. ? table 25, ac characteristics: norm al operation, on page 94: changed t dcbsyr1 (max) from 10s to 5s; added t ccs. ? table 26, program/erase characteristics, on page 95: changed t cbsy (typ) from 3s to 20s. ? figure 78: random data read operation on page 101: changed t whr to t ccs. ? figure 86: program page operation wi th random data input on page 107: changed t adl to t ccs. rev. 1.1, advance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/19/07 ? created separate mlc and slc footer desc riptions and revision numbers; deleted ?mlc:? prefixes; deleted dev/design condit ion, then unconditionalized mlc/slc text where it was identical as a result. ? ?features? on page 1: added 1.0 to onfi, deleted read id2. ? figure 2: part number chart on page 2: deleted 48-pin tsop 1 ocpl wc package code. ? figure 3: pin assignment (top view) 48-pin tsop type 1 on page 9: deleted note 2 re ce3#, ce4#, r/b3#, r/b4#. ? table 10, parameter page data structure, on page 28: added table. ? table 10, parameter page data structure, on page 28: added table. ? ?two-plane page read 00h-00h-30h? on page 53: revised description. draft 5/19/2008 pdf: 09005aef82d68edc / source: 09005aef82d68f88 micron technology, inc., reserves the right to change products or specifications without notice. 8gb_nand_slc_m51a__3.fm -rev. 1.9 5/08 en 118 ?2007 micron technology, inc. all rights reserved. 8, 16, 32, 64gb nand flash memory revision history micron confidential and proprietary advance ? ?two-plane read for internal data move 00h-00h-35h? on page 60: revised description. ? ?interleaved die operations? on page 67: added two-plane page read and inter- nal data move commands. ? former figure 3: interleaved program page with r/b# monitoring on page 63: removed figure and revised description. ? former figure 45: interleaved program pa ge cache mode with r/b# monitoring on page 64: removed figure and revised description. ? former figure 47: interleaved two-plan e program page with r/b# monitoring on page 65: removed figure and revised description. ? former figure 49: interleaved two-plane program page cache mode with r/b# monitoring on page 67: removed figure and revised description. ? former figure 51: interleaved block erase with r/b# monitoring on page 69: removed figure and revised description. ? former figure 53: interleaved two-plane block erase with r/b# monitoring on page 70: removed figure and revised description. ? figure 54: interleaved two-plane block eras e with status register monitoring on page 83: added 78h, address, and status for die 2 to i/ox. ? figure 82: page read cache mode operation without r/b#, part 2 of 2 on page 105: deleted ?don?t cares? from ce#, deleted t ch, t cea. ? former figure 93: 48-pin tsop type 1 ocpl (wc package code) on page 100: deleted figure. rev. 1.0, advance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5/2/07 ? applied condition ?base? to all mlc content to facilitate separation of mlc & slc. no content changes. rev. 1.0, advance. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12/06 ?initial nda release. |
Price & Availability of MT29F8G08AAAC4
 |
|
|
|
|
All Rights Reserved © IC-ON-LINE 2003 - 2022 |
| [Add Bookmark] [Contact Us] [Link exchange] [Privacy policy] |
|
Mirror Sites : [www.datasheet.hk]
[www.maxim4u.com] [www.ic-on-line.cn]
[www.ic-on-line.com] [www.ic-on-line.net]
[www.alldatasheet.com.cn]
[www.gdcy.com]
[www.gdcy.net] |